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研究生： 蕭儒遠
Ju-Yuan Hsiao
論文名稱： 奈米CMOS晶片內序列傳輸之接收器
Nanometer CMOS On Chip Serial Link Receiver
指導教授： 鄭國興
Kuo-Hsing Cheng
周世傑
Shyh-Jye Jou
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 93
語文別： 英文
論文頁數： 83
中文關鍵詞： 奈米 、接收機
外文關鍵詞： Receiver, Nanometer
相關次數： 點閱：9  下載：0 
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    • 在系統單晶片中，設計晶片中的拉線電路十分困難，因為在模組之間的拉線通常會長到5000mm，而且拉線損耗的動態能量在整體晶片中更佔了30%。此論文將從設計者的觀點描述未來拉線的重要性和並提出新的拉線電路。
    因此，我們提出兩種特殊的架構來改善拉線電路的能量損耗和速度，分別是電流感應電路和並列轉序列電路。首先， 我們提出序列式的傳輸應用在晶片內拉線電路上，這種傳輸的好處是很低的拉線複雜度，同時也可比傳統的插入訊號放大器方式省下近60%能量損耗。另外，我們也提出利用電流感應的技術，這種技術可以提供接收端的阻抗匹配同時也達到較高的傳輸頻寬，此外這種技術應用比起電壓感應的技術更加適用於在序列式傳輸上。
    最後，我們提供一個模組分析的工具，可以根據製程的參數、資料傳輸的特性和拉線的長度，提供並且幫助我們設計符合我們所需求的電路。最後，我們分別採用台積電130微米 1P8M CMOS和聯電130微米 1P8M CMOS製程實作出晶片並達到資料速度5Gbps。

    In SOC system design using nano scale CMOS process, it is difficult to design interconnects for low power and high speed. It is because modules may use global interconnects with length up to 5000mm to exchange signals. Besides, 30% of the chip''s dynamic power was consumed by interconnects. In this thesis, we first describe the importance of wires in the future nano scale process and the trend of interconnect link circuit and from designer’s point of view.
    Therefore, we propose two novel schemes to improve the power and speed of interconnect links: current sensing technique and parallel to serial link circuit. First, we propose a serial link technique to reduce power consumption without decreasing throughout. Parallel to serial links has low complexity in routing area and save power consumption up to 60% than optimal repeater insertion method. Besides, we also propose current sensing technique for long interconnects. The advantages of current sensing techniques are: First, current sensing provides suitable impedance in receiver side to match the interconnect impedance which provides higher bandwidth in signal transmission. Second, current sensing amplifier is more suitable than voltage sensing in parallel to serial technology.
    Finally, we develop a power model of interconnect link. According to technology parameter, data activity, and interconnect length, power model will help to decide the exact interconnect parameters to satisfy the performance requirements. Finally, we implement two chips in tsmc 130nm and UMC 130nm to show the performance which data rate can up to 5Gbps.

    Contents Chapter 1 Introduction 1 1.1 Introduction to Network on Chip (NOC) 1 1.2 Motivation and Goals 3 1.3 Thesis Organization 4 Chapter 2 On Chip Interconnect 5 2.1 On Chip Wires 5 2.2 Wire Characteristics 6 2.2.1 Resistance 6 2.2.2 Capacitance 7 2.2.3 Inductance 8 2.3 Conventional On-Chip Circuits 9 2.4 BER and Voltage Noise 11 2.4.1 Reflections 11 2.4.2 Inter-Signal Cross-Talk 12 2.5 New Approaches to Global Interconnect 13 Chapter 3 Current-Sensing Fundamentals 15 3.1 Definition of Current-Sensing 15 3.1.1 Voltage mode 16 3.1.2 Current Mode 16 3.2 Differential Current Sensing 17 3.2.1 Current Sensing Amplifer 18 3.2.2 Modified Current-Sensing Amplifier 22 3.3 Current-Sensing Amplifier with De-Skew Scheme 24 3.4 Comparison of Circuit-Sensing Circuits 28 3.5 Summary 28 Chapter 4 Power Model of Interconnect 30 4.1 Power Model for Three Circuit Types 30 4.1.1 Optimal Repeater Insertion Power Model 32 4.1.2 Differential Voltage-Sensing Power Model 34 4.1.3 Differential Current-Sensing Power Model 36 4.2 Design Parameters of Power Model 38 4.2.1 Voltage Swing 38 4.2.2 Interconnect Width 40 4.2.3 Interconnect Spacing 42 4.2.4 Interconnect Length 43 4.2.5 Data Activity 45 4.2.6 Interconnect Length with Bandwidth 46 4.3 Estimated Interconnect Specifications in VDSM 47 4.4 Summary 49 Chapter 5 Transceiver Design and Implementation 50 5.1 Chip Overview 50 5.2 Receiver 58 5.2.1 Sampler 59 5.2.2 BER Circuit 61 5.3 Implementation 66 5.3.1 tsmc 130nm 66 5.3.2 UMC 130nm 70 5.4 Measurements 72 5.5 Comparisons and Discussions 73 Chapter 6 Conclusions 79 Bibliography 81

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