在本論文中，我們成功製作出利用鋁/銻雙層金屬作為源/汲極的蕭特基接觸的非晶矽(a-Si:H)、非晶矽化鍺(a-SiGe:H)、多晶矽(poly-Si)薄膜電晶體。其中，藉由使用一層很薄的五族金屬銻來取代傳統的n型摻雜，我們可有效率地節省傳統薄膜電晶體的製程步驟進而增加製程效率。
實驗結果顯示，以多晶矽為通道的薄膜電晶體擁有最好的電晶體特性，而在非晶矽的材料中，以非晶矽當通道的元件電性比以非晶矽鍺當通道的元件電性來的優越。在同類的非晶矽鍺薄膜電晶體中，我們發現，當通道中鍺含量越高，電晶體的飽和電流及遷移律會上升而臨限電壓會下降。
最後我們將比較非晶矽(a-Si:H)、非晶矽化鍺(a-SiGe:H)、多晶矽(poly-Si)薄膜電晶體在熱退火處理之後的各種特性，經使用退火處理後發現退火的溫度越高則元件的電性越差。

In this thesis, electrical characteristics of the top-gate staggered TFTs (thin-film transistors) with the Schottky barrier source/drain (S/D) had been studied. The Sb/Al dual metals were evaporated onto channel layer, e.g. a-Si1-xGex:H, or poly-Si, of TFT , where Sb metal was intentionally used as dopant of channel layer, and the electrical characteristics of the obtained TFTs had been compared and analyzed.
For the Schottky barrier S/D (SB-S/D) top-gate a-Si1-xGex:H TFTs, the experimental results indicated that a thinner channel layer could be used to obtain the better current-voltage characteristics of a TFT. Also, the effects of Ge content of a-Si1-xGex:H channel layer and annealing process on the performances of TFTs had been investigated . It was found the device drain current and effective electron mobility would increase, and threshold voltage would decrease with the increasing of Ge content in a-Si1-xGex: H channel. Also, the electrical characteristics of these TFTs became poorer after annealing process.
The electrical characteristics of the SB-S/D top-gate poly-Si TFTs had been also studied. It was found that the obtained poly-Si TFTs had the significantly better electrical characteristics than those of a-Si1-xGex:H TFTs.

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