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研究生: 陳力維
Li-Wei Chen
論文名稱: 二維雙閘極金氧半場效電晶體的探討與模擬
Analysis and Simulation of Two-DimensionalDouble-Gate MOSFET
指導教授: 蔡曜聰
Yao-Tsung Tsai
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度: 100
語文別: 中文
論文頁數: 42
中文關鍵詞: 雙閘極短通道效應
外文關鍵詞: double Gate, short channel effects
相關次數: 點閱:15下載:0
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  • 在本篇論文中,我們將探討雙閘極金氧半場效電晶體的結構,而這結構有以下優
    點:有效抑制短通道效應、低功率消耗、良好的閘極通道控制能力、較好的電流
    驅動力、較低的通道漏電流以及接近理想的次臨限擺幅等。接著我們利用二維元
    件模擬器探討雙閘極金氧半場效電晶體的元件特性,分析雙閘極與單閘極元件的
    Id-Vg 曲線、單閘極與雙閘極在不同通道長度下的次臨限擺幅差異以及雙閘極元
    件在不同體矽厚度下的漏電流。最後,利用臨限電壓公式驗證元件的開發是否正
    確,再來探討改變各種參數對於元件的影響。


    In this thesis, we will investigate the structure of the double-gate MOSFETs. This structure has the following advantages: better short channel effect, low power consumption, good gate-channel control capability, better current driving force, the lower channel leakage current and near ideal sub-threshold swing, etc. Then we design a 2-D device simulator to investigate the device characteristics of the double-gate MOSFET. We analyze the Id-Vg curves of the double gate and single-gate components, sub-threshold swing difference in the different channel length, and double-gate leakage current in the different thickness of the bulk silicon. Finally, we use the threshold voltage formula to verify the validity of the 2-D device simulator,and then analyze the impact of the various design parameters.

    摘要I AbstractII 目錄III 圖目錄IV 表目錄VI 第一章 簡介1 第二章 雙閘極MOSFET介紹與討論3 2-1 做雙閘極MOSFET的原因3 2-2 雙閘極MOSFET的結構8 第三章 雙閘極MOSFET二維模擬器的開發12 3-1 二維等效模擬電路12 3-2 二維的雙閘極MOSFET的基本特性模擬15 3-3 臨限電壓公式與模擬驗證24 第四章 各項參數對雙閘極MOSFET的影響27 4-1 次臨限特性比較28 4-2 改變參數對電流電壓的影響31 第五章結論39 參考文獻41

    [1]D. A. Neamen, “ Semiconductor physics and devices, ”3rd ed., McGraw-Hill Companies Inc., p485~p487, 2005.
    [2]Yuan Taur, “An Analytical Solution to a Double-Gate MOSFET with Undoped Body,” IEEE ELECTRON DEVICE LETTERS,VOL. 21, NO. 5, MAY 2000.
    [3]Leland Chang, Stephen Teng, Tsu-Jae King, Jeffrey Bokor, and Chenming Hu “Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs,”IEDM , 2000,pp719-722.
    [4]Kunihiro Suzuki, Yoshiharu Tosaka, and Toshihiro Sugii, ” Analytical Threshold Voltage Model for Short Channel Double-Gate SOI MOSFET’s, ” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 7, JULY 1996.
    [5]Michael J. Van der To1 and Savvas G. Chamberlain, ” Drain-Induced Barrier Lowering in Buried-Channel MOSFET’s ,“ IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 40, NO. 4, APRIL. 1993.
    [6]Xiaoping Liang, Student Member, ” A 2-D Analytical Solution for SCEs in DG MOSFETs,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 8, AUGUST 2004.
    [7]Hamdy Abd El Hamid, Jaume Roig Guitart, and Benjamin Iniguez, Senior Member, ” Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 6, JUNE 2007.
    [8]Andreas Tsormpatzoglou, Charalabos A. Dimitriadis, Raphael Clerc, G. Pananakakis, and Gerard Ghibaudo, ” Threshold Voltage Model for Short-Channel Undoped Symmetrical Double-Gate MOSFETs,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 9, SEPTEMBER 2008.
    [9]Qiang Chen, Evans M. Harrell, II, and James D. Meindl, ”A Physical Short-Channel Threshold Voltage Model for Undoped Symmetric Double-Gate MOSFETs,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003.
    [10] M. G. C. de Andrade and J. A. Martino, “Threshold voltages of SOI MOSFETs,” Solid-State Electron, vol. 52, no. 12, pp. 1877–1883, Dec.2008.

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