由於IEEE.802.11ad 標準需求高達7 Gbps的數據吞吐速度，也使用較高頻的頻段，造成資料傳輸過程中會有許多通道與雜訊效應影響效能，因此錯誤更正碼的是系統中不可或缺的存在。近年來透過積體技術的蓬勃發展，使得高複雜度的低密度奇偶檢查碼之編碼與解碼方式有了實現的可能，低密度奇偶檢查碼擁有描述簡單並能平行處理的優點，很適合以硬體實現來達成高吞吐率的需求。本文選用支援IEEE 802.11ad 之1/2與3/4兩種碼率的低密度奇偶檢查碼來設計與實作其編解碼器，在編碼器方面運用類循環(QC)-LDPC碼的特性並搭配位移累加暫存器 (Shift Register Adder Accumulator, SRAA)為主體設計出可重配置硬體架構，使用312.5MHz的時脈，可達10Gbps的吞吐率。為了降低複雜度，我們採用了具有疊代性的置信傳播(Belief Propagation)的解碼演算法-最小值總和演算法(Min-Sum Algorithm)，並以行層排程(Column-Based Layer Scheduling)來降低所需的解碼遞迴次數。4大列的行層排程可降低現存洪水式(flooding)的解碼器繞線量巨大的問題，每個時脈周期可更新四分之一的變數節點與所有的檢查節點，四個時脈周期可以完成所有的變數節點更新，內部資料流採用6位元的格式，並發揮行層排程的優勢來節省記憶體的使用量。

IEEE 802.11ad standard supports data rate up to 7Gbps under the 60GHz frequency band. Thus, error correction code is an indispensable component for this communication system. Due to the rapid development of IC technology during these decades, realization of low density parity check code becomes no more intractable. The encoding and decoding of the low-density parity-check code can be processed in parallel, and thus it is very suitable for hardware implementation to accelerate the throughput. In this thesis, design and implementation of an LDPC encoder and decoder that support 0.5 and 0.75 code rates for IEEE 802.11ad are presented. For the encoder design, the properties of QC-LDPC code are exploited and the shift register adder accumulator (SRAA) is employed as the basic functional block. At 312.5 MHz clock frequency, it achieves throughput of 10Gbps. For the decoder design, in order to reduce the complexity, we use the iterative min-sum algorithm derived from the concept of belief propagation as our decoding algorithm and the column-based layer scheduling is also adopted. It takes 4 clock cycles to complete the soft information update of all variable nodes. The column-based scheduling can reduce the huge wire cost of decoders with flooding-based scheduling. Six-bit wordlength is used for internal computation. We also exploit the advantage of the column-based scheduling to save the memory requirements.

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