隨著半導體技術以及SOC ( System-On-Chip ) 的發展，設計電路工作的複雜度亦隨之提升，因此對於設計電路驗證 ( verification ) 的工作也越來越受到重視，而邏輯模擬器 ( logic simulator ) 仍然是目前最廣泛地使用的驗證工具。在驗證過程中，它們給予使用者有完全的觀察度 ( observability )與控制性 ( controllability )，但是若需要用龐大的輸入測試訊號 ( test bench ) 時，則整體的模擬速度將會大大地降低，導致必須浪費冗長的驗證時間。因此，在模擬速度與驗證成本的考量因素下，往往會採用類似仿真器 ( Emulator ) 的現場可程式化閘陣列( Field Programmable Gate Array , FPGA )來完成驗證工作。然而，FPGA在對於驗證工作上完全的觀察度 ( observability ) 卻相當的低，如此造成了功能偵錯上的不便。
因而我們的學長提出了一種以取樣的方式來改善上述的這些問題。對於此方法的主要想法，在整個模擬的過程中，它會記錄FPGA內部的行為，然後對於我們所想要觀察偵錯的波形區段，則將會在邏輯模擬器上重新播放模擬結果。如此我們大部份的模擬過程都花費在FPGA上，故使用者不但得到高速的好處，而且對於電路的完全觀察度及控制性則可在軟體的邏輯模擬器上獲得。
在本篇論文中，我們針對於這個方法更進一步地加以改善，在紀錄FPGA內部訊號，我們不再需要紀錄內部所有的節點訊號，而是依據一個抓取的準則來決定哪些節點才是我們必要抓取的，因此我們又可以降低所需要記錄的資料量，以提升硬體資源使用的效率。最後我們由實驗結果證實，我們所提之方法的效率。

[1] Cadence Design System Corporation., Palladium Data sheet, http://www.cadence.com/datasheets/4510C_IncisivePalladium_fnl.pdf
[2] Mentor Graphics Corporation, Vstation Pro Emulator, http://www.mentor.com/vstation/vstation_pro.html
[3] IEEE, Standard 1149.1a, IEEE standard Test Access Port and Boundary-Scan Architecture, revised, 1993.
[4] Altera Corporation, Signal Tap II Embedded Logic Analyzer, http://www.altera.com/products/software/pld/design/verification/signaltap2
/sig-index.html
[5] Xilinx Corporation, Chip Scope On Chip Debug Integrated Logic Analyzer, http://www.xilinx.com/ise/verification/chipscope_pro_glance2.htm
[6] Anurag Tiwari, Karen A. Tomko, “Scan-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs”, ASPDAC, 2003.
[7] Joshua Marantz, “Enhanced Visibility and Performance in Functional Verification by Reconstruction”, Proc. DAC’98, San Francisco, CA
[8] ITC’99 test suite, Electric CAD & Reliability Group, http://www.cad.polito.it/tools/#bench
[9] Temento Corporation, DiaLite Instrumentation for Verification on FPGAs, http://www.temento.com/solutions/fpga.php
[10] Michael L. Bushnell and Vishwani D. Agrawal, “Essentials of Electronic Testing”, Kluwer Academic Publishers, 2000.
[11] Xilinx Corporation, Readback Function, XAPP138 : Virtex Configuration and Readback, http://www.xilinx.com/ipcenter/catalog/search/reference
/xapp138_virtex_configuration_and_readback.htm
[12] Agilent Technologies, Trace Port Analyzer for On Chip Design Verification With Xilinx FPGAs, http://cp.literature.agilent.com/litweb/pdf/5988-9434EN.pdf
[13] Altera Corporation, Quartus ⅡDesign Software for Altera FPGAs, http://www.altera.com/literature/manual/intro_to_quartus2.pdf
[14] Model Technology Corporation, ModelSim 5.5 e, Simulation Software, http://www.model.com/products/se.asp
[15] Altera Corporation, Nios Development Board_APEX Edition, http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
[16] Altera Corporation, ByteBlasterMV Parallel Port Download Cable, http://www.altera.com/literature/ds/dsbytemv.pdf
[17] Integrated Device Technology, Data Sheet of 3.3 V CMOS Asynchronous SRAM, http://www1.idt.com/pcms/tempDocs/71V016_DS_6428.pdf
[18] Flottes, M. L., Pires, R., Rouzeyre, B., Volpe, L., “Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique”, Design, Automation and Test in Europe, 1998.
[19] Mukherjee, D., Pedram, M., Breuer, M., “Control Strategies for Chip-based DFT/BIST Hardware”, Test Conference, 1994.
[20] Chih-Chang Lin, Marek-Sadowska, M., Lee, M. T.-C., Kuang-Chien Chen, “Cost-free Scan: A Low Overhead Scan Path Design”, Computer-Aided Design of Integrated Circuits and Systems”, 1998.
[21] Verisity Corporation, Xcite Simulation Acceleration platform, http://www.verisity.com/products/xcite.html
[22] Dong Jung Lu, “ A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA ”, Master of Science in Electrical Engineering in the graduate division of the National Central University, June 2004.
[23] Chien-Nan Jimmy Liu, I-Ling Chen, and Jing-Yang Jou, " An Efficient Design-for-Verification Technique for HDLs ", ACM/IEEE Asia and South Pacific Design Automation Conference (EI), pp. 103-108, January 2001.
[24] Chien-Nan Jimmy Liu, " A Design-for-Verification Technique for Reducing Debugging Efforts in HDL ", the Eleventh Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 33-38, April 2003.