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研究生： 張力煒
Li-wei Chang
論文名稱： 可支援2×2~4×4 MIMO系統之高速實數及複數Sorted QR分解
Design of High Speed Sorted QR Decomposition for 2×2~4×4 MIMO Detectors
指導教授： 薛木添
Muh-tian Shiue
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 100
語文別： 中文
論文頁數： 76
中文關鍵詞： 排序 、QR分解
外文關鍵詞： MIMO, Sorted QR, SQRD
相關次數： 點閱：17  下載：0 
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    • 本論文以傳統Sorted QR分解來分析其各級排序造成的能量分佈情形，並且探討排序後對於後端樹狀解碼中每一層所造成的影響，之後再依據我們的搜尋方式將效能較差的排序級數跳過，找到一個複雜度最低且錯誤率無明顯上升的排序組合。在QR分解的架構中我們採用Systolic Array的架構來達到較高的產出量，並且加入輸入控制電路使其能夠支援不同天線數的QR分解，使硬體使用率盡可能地提高。相較於傳統Sorted QR分解，我們所提出的方法除了有較低的排序複雜度外，在於運算時間上也能有相當的改善，我們以所提出的方法設計我們的電路架構使其能更有效率運算。最後本論文使用SMIMS VeriEnterprise Xilinx FPGA板驗證其電路功能，並且以TSMC-90 nm製程實現所提出之QR分解電路。

    This thesis is dedicated to analyze the circumstance of energy distribution which is caused by different sorting stages with conventional Sorted QR decomposition. It also discusses the effect of each stage of Sphere decoder after sorting. Furthermore, according to our searching methods, tries skip the inefficient sorting stages and then find out a sorting combination which is less complicated and which doesn’t have an apparently rising sorting combination.
    In the structure of QR decomposition, we adapt Systolic Array structure in order to achieve a higher production, and also add input control for supporting different antenna mode of QR decomposition for the sake of raising the utility rate as possible as we can. In comparison with the conventional Sorted QR decomposition, our method is not only less complicated, but also has a great extent of improvement of operating time. We design our architecture with this method for having a more efficient operation.
    In the end, we use MIMS VeriEnterprise Xilinx FPGA to verify circuit function, then we use TSMC-90 nm to implement our circuit.

    第一章 緒論 1 1.1 系統介紹 1 1.1.1 MIMO系統模型 1 1.1.2 空間多工(Spatial Multiplexing) 2 1.2 研究動機 2 1.3 論文架構 3 第二章 QR分解介紹與比較 4 2.1 QR分解概述 4 2.1.1 複數系統之QR分解介紹 4 2.1.1 實數系統之QR分解介紹 4 2.2 QR分解演算法分類 5 2.2.1 Gram-Schmidt 5 2.2.2 Householder 7 2.2.3 Givens Rotation 8 2.2.4 以CORDIC實現Givens Rotation 10 2.2.4.1 CORDIC演算法介紹 10 2.2.4.2 vectoring mode 與 rotating mode介紹 12 2.2.4.3 CORDIC電路介紹 15 2.3 QR分解架構分類 16 2.3.1 記憶體式架構 16 2.3.2 Systolic Array架構 17 2.3.2.1 實數Systolic Array QR分解電路介紹 18 2.3.2.2複數Systolic Array QR分解電路介紹 19 2.3.3 架構比較 20 第三章 所提出之Sorted QR 分解 21 3.1 Sorted QR介紹 21 3.2傳統Sorted QR分解主要問題 22 3.3所提出之Sorted QR分解演算法 25 3.3.1傳統SQRD中排序複雜度分析 25 3.3.2各種排序組合比較 27 3.3.3 所提出之Sorted QR 分解 33 3.4 Sorting 複雜度比較 45 第四章 所提出之Sorted QR分解電路設計 46 4.1 設計課題 46 4.2 硬體架構 47 4.3 Systolic Array QR分解電路設計 48 4.3.1 本論文之CORDIC設計 51 4.4 Sorting 電路設計 53 4.4.1 MCF電路設計 55 4.4.2 NC電路設計 57 4.5所提出之SQRD與傳統SQRD架構比較 59 第五章 晶片實現 62 5.1 設計流程 62 5.2 定點數分析 63 5.3 FPGA驗證 67 5.4 晶片設計結果 69 5.5 硬體比較 73 第六章 結論 74 參考文獻 75

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