低能量時脈儲存元件之分析、設計與量測｜國立中央大學博碩士論文系統

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研究生：	余美儷 Mei-Li Yu
論文名稱：	低能量時脈儲存元件之分析、設計與量測 Analysis, Design and Measurement of Low-Energy Clocked Storage Elements
指導教授：	鄭國興 kuo-Hsing Cheng 周世傑 Shyh-Jye Jou
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	94
語文別：	中文
論文頁數：	119
中文關鍵詞：	漏電流控制、低功率雙緣觸發正反器、量測電路
外文關鍵詞：	leakage control, low power double edge triggered DFF, test circuit
相關次數：	點閱：10 下載：0
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由於可攜式電子產品的需求量增加以及其要求的效能提升，因此設計低功率消耗已成為積體電路設計重要理念。隨製程由微米進入奈米時代，觀察其漏電流對功率消耗之影響趨勢。利用結合準位轉換器與雙緣觸發正反器和應用雙臨界電壓元件之技巧，我們提出一個新的低功率正反器以及控制漏電流之設計。本論文中，我們提出一個新型且超低功率正反器，其功率消耗與其他的正反器相比至少降低了27%。並將其應用在管線式系統中，得以有效降低功率消耗。低功率正反器之模擬與量測結果是使用台積電0.13 微米1P8M CMOS 製程完成，最後我們以量測時序及模擬電流之結果為依據，證明我們提出的電路為低功率、高可靠
度之設計。
針對未來高速度、低面積、低功率、低雜訊之電路性能要求，我們實現晶片內可量測時脈儲存元件之精確延遲時間特性、功率消耗以及製造與估計內部電壓源抖動量值之電路設計。此架構具有4.3ps 的時間特性解析度及控制0.05V 之電壓源抖動雜訊，將此量測電路實現於聯電0.13 微米1P8M CMOS 製程，藉此證明我們提出的方法，能夠量測晶片內時脈儲存元件精準之時間特性、實際功率消耗以及估計電壓源抖動雜訊量值。

第1 章 簡 介.............................................................. 1
1 實現低功率正反器之動機與目的...........................................1
2 低功率電路設計技巧.....................................................2
2.1 結合準位轉換器與正反器之技巧.........................................3
2.2 雙電壓源及雙臨界電壓元件之設計.......................................4
2.3 雙緣觸發正反器應用於管道式系統.......................................5
3 量測電路之概念與簡介...................................................6
4 章節概要介紹...........................................................6
第2 章 低功率線路階層之分析與設計......................................... 8
1 CMOS 之電路功率消耗....................................................8
1.1 電晶體基板之漏電流..................................................10
1.2 逆向二極體漏電流....................................................11
1.3 電晶體之閘極漏電流..................................................12
2 降低正反器功率之技巧..................................................19
2.1 電源壓之改變........................................................19
2.2 低擺幅電路設計技巧..................................................22
3 降低時脈訊號擺幅之正反器設計技巧......................................23
3.1 半擺幅之時脈訊號設計................................................24
3.2 降一個臨界電壓之時脈訊號設計........................................25
第3 章 雙臨界電壓之雙緣觸發與資料/時脈準位轉換之正反器應用............... 27
1 正反器之時序運作......................................................27
1.1 脈衝觸發正反器......................................................27
1.2 主奴式正反器........................................................29
2 正反器之時序及延遲時間................................................30
2.1 設定/保持/傳遞延遲時間..............................................30
3 正反器模擬考量........................................................33
3.1 輸入緩衝器..........................................................33
3.2 輸出負載............................................................34
4 應用雙臨界電壓之設計..................................................35
5 雙緣觸發正反器........................................................39
5.1 單一相位之資料及時脈訊號雙緣觸發架構................................39
5.1.1 單一相位雙緣觸發時脈訊號架構......................................39
5.1.2 輸出分開之單一相位時脈訊號架構....................................41
5.2 單一相位資料及正反相位時脈訊號之雙緣觸發架構........................42
5.2.1 正反相位時脈訊號之雙緣觸發正反器..................................42
5.2.2 動態C²MOS 架構....................................................43
5.3 正反相位資料及時脈訊號之雙緣觸發正反器..............................44
5.3.1 差動輸入訊號架構..................................................45
5.3.2 提出改善功率消耗之電路架構........................................46
5.4 低擺幅時脈訊號之雙緣觸發正反器......................................46
5.4.1 低擺幅時脈訊號之雙緣觸發正反器....................................47
5.4.2 互斥或閘組成之雙緣觸發正反器......................................49
5.5 低擺幅時脈與資料之雙緣觸發正反器....................................50
5.5.1 應用雙電壓源與雙臨界電壓元件之雙緣觸發正反器......................50
5.5.2 我們提出降低功率之電路............................................52
6 設計驗證電路架構之考量................................................54
7 電路之模擬及分析......................................................56
7.1 第一種雙緣觸發正反器................................................57
7.2 第二種雙緣觸發正反器................................................58
7.3 第三種雙緣觸發正反器................................................59
7.4 第四種負緣觸發正反器................................................60
8 設計佈局驗證電路之模擬結果............................................62
8.1 加入打線考量之模擬結果..............................................63
8.2 整體電路佈局與預計結果..............................................64
9 量測結果之分析........................................................66
第4 章 時脈儲存元件特性之量測電路........................................ 73
1 簡述量測元件特性電路之未來應用........................................73
2 介紹具有高解析之時序分析電路架構......................................74
2.1 延遲元件之電路設計..................................................76
2.2 延遲時序之基準訊號產生器............................................79
2.3 延遲路徑之設計......................................................83
3 電路內部可量測和製造電壓源抖動雜訊之設計..............................84
4 可量測實際電路功率消耗之設計..........................................94
5 實現可量測元件特性電路之結果分析......................................96
第5 章 結 論............................................................ 102
參考資料................................................103

                                

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