具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器

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研究生：	涂祐豪 Yo-hao Tu
論文名稱：	具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器 A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier
指導教授：	鄭國興 Kuo-hsing Cheng
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	99
語文別：	中文
論文頁數：	78
中文關鍵詞：	阻塞鎖定、責任週期校正電路、半穿透式架構、頻率倍頻器、延遲鎖定迴路
外文關鍵詞：	Stuck Locking, Frequency Multiplier (FM), Half Transparent (HT), Duty Cycle Corrector (DCC), Delay-Locked Loop (DLL)
相關次數：	點閱：15 下載：0
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　　本論文提出一個具寬頻操作、擁有多個相位輸出並具有相位誤差較正電路的延遲鎖定迴路。為了得到更大的運用效能，還具有一個頻率倍頻器可以另外產生一個倍頻的時脈訊號。在延遲鎖定迴路中，利用多頻段技巧，使電路可以操作在較寬的操作頻帶之下。而為了減少因為靜態相位誤差帶來的效應，利用一個時間放大器所組成的校正迴路，可以達到修正相位誤差的效果。延遲鎖定迴路整體電路架構若要操作在高速之下，在設計上有一定的難度，故將架構中的多相位輸出，透過邊緣合成的技巧，即可得到一個高速的時脈訊號，而延遲鎖定迴路本身卻可以保持較低速的操作頻率。另外，延遲鎖定迴路之多相位輸出可提供給發射端電路(Transmitter, Tx)使用，作為其時脈產生器。
　　本論文之具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器使用TSMC 180 nm 1P6M CMOS製程實現晶片，其操作頻率範圍可從80 MHz到600 MHz，並且擁有12個相位的輸出，而頻率倍頻器範圍可從0.96 GHz 到 2.5 GHz。整體晶片面積為745 × 745 um2，核心電路的面積為356 × 356 um2。電路在操作電壓為1.8 V時，最大功率消耗為19.2 mW。延遲鎖定迴路輸出訊號(600 MHz)之最大抖動量(P2P Jitter)的為21.22 ps，方均根抖動量(RMS Jitter)為2.62 ps。而頻率倍頻器的輸出訊號(2.4 GHz)之最大抖動量(P2P Jitter)為35.11 ps，方均根抖動量(RMS Jitter)為4.28 ps。本論文提出的改良式責任週期校正電路和相位誤差補償迴路皆能有效的操作，並且相位誤差可以得到約 33.33 % 的改善。

　　This study presents a wide-range and multiphase DLL-based clock generator with the Phase Error Compensation loop. For more applications, we proposed a frequency multiplier to synthesize a combined clock. In this voltage control delay line, we take the multi-gain technique to achieve the wide-range operation frequency. And we proposed a Phase Error Compensation loop with the timing amplifier. It is difficult to realize a DLL in high operation frequency, so using multiphase technique can solve this problem. And the multiphase architecture can become the clock generator of a Transmitter (Tx).
　　This study was implemented by TSMC 180 nm 1P6M CMOS process. The input frequency range of the proposed DLL is from 80 MHz to 600 MHz with 12-phase output. The output range of frequency multiplier is from 0.96 GHz to 2.5 GHz. The chip area is 0.745 × 0.745 mm2 and the core area is 0.356 × 0.356 mm2. The power consumption is 19.2 mW at a supply of 1.8 V. The peak-to-peak jitter and rms jitter of delay locked loop are 21.22 ps and 2.62 ps at 800 MHz. The peak-to-peak jitter and rms jitter of frequency multiplier are 35.11 ps and 4.28 ps at 2.4 GHz. And the Phase Error Compensation loop can improve 33.33% of the static phase error.

Abstract .......................................................................................................................... ii
目錄................................................................................................................................ iii
致謝................................................................................................................................ vi
圖目錄............................................................................................................................ vii
表目錄............................................................................................................................ ix
第1章 緒論..................................................................................................................... 1
1 研究動機.................................................................................................................. 1
2 發射端電路.............................................................................................................. 2
3 論文架構.................................................................................................................. 4
第2章 延遲鎖定迴路架構與理論................................................................................. 5
1 傳統類比式延遲鎖定迴路架構.............................................................................. 5
1.1 相位偵測器........................................................................................................... 6
1.2 充電幫浦與迴路濾波器....................................................................................... 7
1.3 電壓控制延遲線................................................................................................... 8
1.3.1 電阻電容時間常數控制式延遲元件................................................................ 9
1.3.2 可變電容式延遲元件[2] ................................................................................... 9
1.3.3 電流限制式延遲元件[2] ................................................................................... 10
1.3.4 差動對稱性負載式延遲元件............................................................................ 11
2 延遲鎖定迴路之理論分析...................................................................................... 12
2.1 錯誤鎖定............................................................................................................... 12
2.2 鎖定範圍............................................................................................................... 13
2.3 系統分析............................................................................................................... 14
2.4 行為模型............................................................................................................... 15
第3章 改良式相位偵測器與相位誤差補償迴路......................................................... 17
1 介紹.......................................................................................................................... 17
2 半穿透架構式相位偵測器問題探討...................................................................... 17
2.1 半穿透架構式相位偵測器................................................................................... 17
2.2 半穿透架構式相位偵測器的錯誤狀況............................................................... 18
3 改良式相位偵測器.................................................................................................. 21
3.1 改良式責任週期校正電路(MDCC) .................................................................... 21
3.2 具有改良式責任週期校正電路的相位偵測器................................................... 22
4 相位誤差補償.......................................................................................................... 26
4.1 時間放大器........................................................................................................... 26
4.2 相位誤差補償電路............................................................................................... 28
第4章 具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器......................... 31
1 介紹.......................................................................................................................... 31
2 電路架構與系統分析.............................................................................................. 32
3 電路設計.................................................................................................................. 33
3.1 充電幫浦............................................................................................................... 33
3.2 電壓控制延遲線................................................................................................... 34
3.3 頻率倍頻器........................................................................................................... 38
3.4 跳段機制............................................................................................................... 40
3.5 拴鎖鎖定保護電路............................................................................................... 42
第5章 晶片模擬與量測................................................................................................. 45
1 電路佈局.................................................................................................................. 45
2 電路模擬.................................................................................................................. 46
2.1 自動跳段模擬圖................................................................................................... 46
2.2 多相位輸出和相位抖動模擬圖........................................................................... 48
3 量測環境考量.......................................................................................................... 51
4 晶片與印刷電路板照相.......................................................................................... 54
5 量測結果.................................................................................................................. 55
6 規格比較.................................................................................................................. 59
第6章 結論與未來研究方向......................................................................................... 61
1 結論.......................................................................................................................... 61
2 未來研究方向.......................................................................................................... 61
參考文獻........................................................................................................................ 62

                                

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