目前國內半導體業者正積極投入設立12 吋晶圓廠，而半導體產業是屬於高資本投資的產業，興建一座半導體晶圓製造廠往往需要至少五至七佰億新台幣，且隨著新製程的改善，其所需的投資成本亦會隨著增加；再加上台灣土地狹小，價格昂貴，取得越來越不容易，以及晶圓廠本身的一些特性如廠房地板下需埋設管線設備以及晶圓製造的加工途程，具有高度的迴流（Reentrant），造成物料搬運活動非常頻繁，如果以傳統人工搬運車搬運晶圓，則效率必然低落等特性，使得晶圓廠一旦完工後，日後若想更改原始佈置顯得困難重重。因此，晶圓製造廠的佈置方式以及自動化搬運系統的配置在初期規劃階段就顯得格外的重要。
半導體產業中物流最佳化設計的目的是在於減少晶圓搬運損傷、提高良率及生產量、降低cycle time、減低在製品存量及縮短交期，因此，如何規劃出更有效率的廠房佈置，將有限的空間做最有效率的運用，進而提高生產績效、降低成本，成為現代製造系統中重要的一環，也成為企業獲益的重要因素。
本研究的主要動機在於運用設施規劃的方式，針對現有晶圓廠設施佈置及自動化物料搬運系統配置進行佈置改善，並透過啟發式演算法與數學模型來縮短晶圓間的搬運距離用以解決晶圓廠中Interbay系統的物料搬運問題，希望在考慮求解時間及解答品質下，得到一個最佳的佈置方案。同時更可以因為減少晶圓搬運距離而提高機器設備的使用率，並且降低晶圓的製造以及搬運成本。本研究將針對『晶圓廠內設施規劃』中『脊椎式』和『外圍式』混合的設施規劃問題做有系統的規劃與佈置。

In recent years, semiconductor manufacturing (SM) companies enthusiastically establish 300-mm fabs. However, establishing a new SM facility needs at least multi-billion US dollars. With the limited area in Taiwan, large footprints not only pose constraints for the facility designer but present challenge in the design of automatic material handling system (AMHS). SM is a highly sophiscated operation with various processes to be performed, and SM factories typically have reentrant flow to introduce the incresed number of process steps. In response to such challenge, it has become necessary to eliminate the manual handling of the wafers. As a result, facility layout design and AMHS are two major aspects to achieve a sucessful 300-mm fab.
The purpose of the optimazation of material transport is to reduce cycle time, work in process (WIP), delivery time, and increase yield. Therefore, the approach attepmpted to incorporate facility layout and AMHS simulataneously has become a critical factor on factory operation.
This paper focuses on using the integrated fab layout to achieve a short transportation distance of interbay by employing heuristic algorithm and mathematical programming model. In addition, this paper proposes this two-stage procedure can obtain a good quality solution. Based on this analysis, effective facility layout is shown to reduce tansportation distance of wafer lots, and increase equipment utility. This pape will mainly aimed double-loop configuration(which is blend spine-configuration with Perimeter-configuration) facility layout problem.

英文部分
1. Abdinnour-Helm, S., and Hadley, S. W., 2000, “Tabu search based heuristics for multi-floor facility layout,” International Journal of Production Research, vol. 32, no.2, pp. 365-383.
2. Abdou, G., and Dutta, S. P., 1990, “An integrated approach to facilities layout using expert systems,” International Journal of Production Research, vol. 28, no. 4, pp. 685-708.
3. Badiru, A. B.,and Arif, A.,1996, “Facility layout expert system using fuzzy linguistic relationship codes,” IIE transactions . Vol. 28, no. 4, pp. 295-308.
4. Balakrishnan, J., Cheng, C. H., and Wong, K. F., 2003, “FACOPT：a user friendly facility layout optimization system,” Computer and Operations Research, vol. 30, no. 11, pp. 1625-1641.
5. Banerjee, P., and Zhou, Y., 1995, “Facilities layout design optimization with single loop material flow path configuration,” International Journal of Production Research, vol. 33, no. 1, pp. 183-203.
6. Baykasoglu, A., and Gindy, N. N. Z., 2001, “A simulated annealing algorithm for dynamic layout problem,” Computer and Operations Research, vol.28, no. 14, pp. 1403-1426.
7. Bozer, Y. A., Meller, R. D., and Erlebacher, S. J., 1994, “An improvement-type layout algorithm for single and multiple-floor facilities,” Management Science, vol.40, no.7, pp. 918-932.
8. Campbell, P. L. and Laitinen, G., 1997, “Overhead intrabay automation and microstocking-A virtual fab Case Study,” Advanced Semiconductor Manufacturing Conference and Workshop, IEEE /SEMI, pp. 368-372.
9. Cardarelli, E. and Pelagagge, P. M., 1995, “Simulation tool for design and management optimization of automated interbay material handling and storage systems for large wafer web,” IEEE Transactions on Semiconductor Manufacturing, vol.8, no.1, pp. 44-49.
10. Cardarelli, G., Marcello, P. and Granito, A., 1996 ,“Performance analysis of automated interbay material handling and storage systems for large wafer fab”, Robotics & Computer-Integrated Manufacturing, vol.12, no.3, pp. 227-234.
11. Carrie, A. S., 1980, “Computer-aided layout planning - the way ahead,” International Journal of Production Research, vol. 18, no. 3, pp. 283-297.
12. Chae, J. J., and Peters, B.A., 2006, “A simulated annealing algorithm based on a closed loop layout for facility layout design in flexible manufacturing systems,” International Journal of Production Research, vol. 44, no. 13, pp. 2561-2572.
13. Chang, C. F., and Chang, S. K., 1998, “A layer-based approach for semiconductor fabrication facilities,” Advanced Semiconductor Manufacturing Conference and Workshop, IEEE/SEMI, pp. 385-390.
14. Chen, C. W., and Sha, D. Y., 2005, “Heuristic approach for solving the multi-objective facility layout problem,” International Journal of Production Research, vol. 43, no. 21, pp. 4493-4507.
15. Chiang, W. C., and Kouvelis, P., 1996, “An improved tabu search heuristic for solving facility layout design problems,” International Journal of Production Research, vol. 34, no. 9, pp. 2565-2585.
16. Chick, S., S