以 RFSoC平台設計與實現DVB-S2訊號數位中繼器｜國立中央大學博碩士論文系統

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研究生：	康栚洲 JEN-JOU KANG
論文名稱：	以 RFSoC平台設計與實現DVB-S2訊號數位中繼器 Design and Implementation of Digital Repeater for DVB-S2 Signal with RFSoC Platform
指導教授：	陳逸民 YI-MIN CHEN
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 通訊工程學系 Department of Communication Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	中文
論文頁數：	111
中文關鍵詞：	第二代數位廣播、數位中繼器、收發機、RFSoC 、軟體定義無線電、FPGA
外文關鍵詞：	Digital Video Broadcasting-Satellite-Second Generation, Digital Repeater, Transceiver, RFSoC, Software-defined-radio, FPGA
相關次數：	點閱：25 下載：0
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近期以低軌道通訊衛星群提供全球隨時隨地高資料率行動上網技術成為熱門的研究課題與技術發展方向，於是採用第二代數位廣播 (DVB-S2)，除了QPSK，更提供 8PSK、16APSK、32APSK等多種調變方式，更能適應線性特性相對不好的衛星傳輸通道。
本論文在RFSoC平台實現DVB-S2之收發機。在發射機中，包含了BCH code、LDPC code和調變器，接收機則包含時間同步、頻率同步、相位同步，時間同步採用內插器，以消除時序偏移並進行同步取樣，頻率同步則是以固定星座圖去計算及修正頻率偏移，相位同步則是以已知的Start Of Frame (SOF) 來修正相位，並增加自動偵測調變機制 (MODCOD-Detector) ，以便後續解碼器所用，將其整合實現DVB-S2收發機。並實現數位中繼器 (Digital Repeater) 的應用，可應用在衛星酬載中用以重新產生任意調變及碼率之訊號，獲取之訊號放大以及重新產生，使得訊號恢復強度以及質量，降低傳輸時訊號衰減以及失真的影響在高速傳收上增進訊號之品質。

Recently, providing high data rate mobile internet access anytime and anywhere through low Earth orbit communication satellite networks has become a popular research topic and technical development direction. The second-generation digital broadcasting (DVB-S2) is adopted, which provides multiple modulation methods such as QPSK, 8PSK, 16APSK, and 32APSK to adapt to satellite transmission channels with relatively poor linear characteristics.

This paper implements a DVB-S2 transceiver on the RFSoC platform. The transmitter includes BCH code, LDPC code, and modulator, while the receiver includes time synchronization, frequency synchronization, and phase synchronization. Time synchronization uses an interpolator to eliminate timing offset and perform synchronous sampling. Frequency synchronization uses a fixed constellation diagram to calculate and correct frequency offset. Phase synchronization corrects the phase using the known Start Of Frame (SOF) and adds an automatic modulation code (MODCOD-Detector) detection mechanism for subsequent decoder use, integrating it into the DVB-S2 transceiver implementation. The paper also implements the application of a Digital Repeater, which can be used in satellite payloads to regenerate signals of any modulation and code rate. The obtained signal is amplified and regenerated, restoring signal strength and quality, improving signal quality for high-speed transmission and reception, and reducing the effects of signal attenuation and distortion during transmission.

中文摘要  i
Abstract  ii
目錄  iii
圖目錄  iv
表目錄  v
第一章 緒論    1
1  研究動機與背景    1
2  章節簡介    2
第二章 DVB-S2規格簡介    3
1  DVB-S2流程架構    3
2  Frame架構    4
2.1  FEC Frame    4
2.2  PL Frame    6
2.3  PL Header    7
3  Frame內部建構運作    8
3.1  Bit Interleaver    8
3.2  PL Scrambling    10
4  Bit Mapping    11
4.1  QPSK    11
4.2  8PSK    11
4.3  16APSK    12
4.4  32APSK    13
第三章 DVB-S2收發機系統    14
1  發射端編碼處理    14
1.1  BB Scrambling    14
1.2  BCH Encoder    15
1.3  LDPC Encoder    16
1.4  Bit Interleaver    16
2  Constellation Mapping    18
3  PLHeader    18
4  適應編碼調製機制    20
4.1  DVB-S2發射端架構與參數    20
4.2適應編碼調製機制    21
5  升降取插值濾波器(Up-Down sample Interpolation Filter)    23
6  接收端流程架構    24
6.1  接收端架構    24
6.2  接收端訊號模型    24
7  再取樣(Resampling)    27
7.1  費洛內插器(Farrow Interpolator)    27
7.2  Cubic Lagrange Interpolator    29
8  匹配濾波器(Matched Filter)    30
9  符碼同步(Symbol Synchronization)    31
9.1  符碼同步原理架構    33
10  載波同步(Carrier Synchronization)    35
10.1  DVB-S2訊號規格Hard-Decision    36
10.2  載波同步原理架構    40
11  Frame同步    41
11.1  相關器(correlator)    41
11.2  Descrambling    44
12  自動偵測調變    45
13  自動增益控制(Automatic Gain Control)    46
第四章 硬體架構實現    48
1  Squar Root Raise Cosine    48
1.1  Poly phase    48
1.2  SRRC模組    49
1.3  SRRC架構    50
1.4  升降取插值濾波器    51
1.5  升降取插值濾波器架構    53
2  符碼同步模組    54
2.1  Farrow Interpolator    55
2.2  Timing Error Detector    59
3  載波同步模組    60
3.1  Decision-Directed Phase-Error Estimator    61
3.2  Loop filter(carrier synchronization)    62
4  Frame同步與相位同步模組    62
4.1  相關器(Correlator)    63
4.2  自動偵測調變(MODCOD Detector    64
4.3  量化處理訊號bits數    64
4.4  MODCOD 相關器乘法簡化處理    66
5  自動增益控制(Automatic Gain Control)    68
 
第五章 RFSoC平台之實現    70
1  RFSoC(射頻系統單晶片)    70
2  RFSoC平台    71
2.1  RFSoC DAC/ADC    72
2.2  RFSoC Clock    75
3  DVB-S2 Digital Repeater    77
3.1  Repeater 執行流程圖    78
3.2  Repeater Buffer Engine    79
3.3  Repeater取樣率偏差之影響    81
3.4  Repeater個別模組之延遲    83
4  實驗結果    84
4.1  系統使用資源    85
4.2  收發機硬體實現結果    90
4.3  Repeater硬體實現結果    92
第六章 結論    95
參考文獻     96


                                

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