DVB-S2(X) LDPC高資料率解碼器之FPGA設計、實現與驗證

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研究生：	劉亦軒 Yi-Hsuan Liu
論文名稱：	DVB-S2(X) LDPC高資料率解碼器之FPGA設計、實現與驗證 Design, Implementation and Verification of High Throughput DVB-S2(X) LDPC Decoder with FPGA
指導教授：	陳逸民
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 通訊工程學系 Department of Communication Engineering
論文出版年：	2023
畢業學年度：	112
語文別：	中文
論文頁數：	101
中文關鍵詞：	低密度奇偶檢查碼、QC-LDPC 、Min-Sum演算法、LDPC解碼器、FPGA 、ZCU111 、第二代數位衛星廣播
相關次數：	點閱：7 下載：0
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第二代數位衛星廣播(DVB-S2(X))在現代通訊領域扮演著重要角色，在通道編碼方面，使用BCH碼作為外碼，LDPC碼作為內碼，用兩種錯誤更正碼組合，以提供更好的糾錯與更正能力。
本論文研究內容為解決硬體解碼效能不如軟體解碼效能之問題，提升LDPC解碼器的資料吞吐率，並加入DVB-S2X Short Frame的規格，使原先只支援DVB-S2規格的LDPC解碼器可支援DVB-S2(X)規格，再以Xilinx的RFSoC ZCU111實現與驗證DVB-S2(X)規格的LDPC解碼器。解碼使用的演算法為硬體複雜度較低的Min-Sum演算法。由於DVB-S2(X)之LDPC校驗矩陣可排列成為QC(Quasi-Cyclic)-LDPC校驗矩陣，故設計上使用適用於QC-LDPC且平行處理資料的硬體架構。此外，LDPC解碼器可以透過參數及控制訊號的配合進行對應的解碼模式。

The second generation of digital satellite broadcasting (DVB-S2(X)) plays a crucial role in the modern communication domain. In terms of channel coding, it utilizes BCH code as the outer code and LDPC code as the inner code, combining two error correction codes to provide enhanced error detection and correction capabilities.
The research focus of this thesis is to address the issue of hardware decoding performance lagging behind software decoding, aiming to enhance the data throughput of the LDPC decoder. Additionally, the DVB-S2X Short Frame specification is incorporated, enabling the LDPC decoder that originally supported only DVB-S2 specifications to accommodate DVB-S2(X) specifications. The implementation and verification of the DVB-S2(X) LDPC decoder are carried out using the Xilinx RFSoC ZCU111. The decoding algorithm employed is the Min-Sum algorithm with lower hardware complexity. Given that the LDPC parity-check matrix of DVB-S2(X) can be rearranged into a Quasi-Cyclic (QC) LDPC parity-check matrix, the hardware architecture is designed to be suitable for QC-LDPC and parallel data processing. Moreover, the LDPC decoder can adapt its decoding mode through the coordination of parameters and control signals.

摘要        i
Abstract    ii
誌謝        iii
目錄        iv
圖目錄        vii
表目錄        xi
第一章、    緒論    1
1    研究動機與背景    1
2    章節簡介    2
第二章、    LDPC Code    3
1    LDPC Code介紹    3
2    線性區塊碼(Linear Block Code)    3
3    DVB-S2(X)之LDPC規格    5
4    LDPC編碼    7
5    Tanner Graph    8
6    LDPC解碼    8
6.1    Sum-Product Algorithm    9
6.2    Min-Sum Algorithm    13
第三章、    硬體實現LDPC解碼器    16
1    Modified Min Sum Algorithm    16
2    Quasi-Cyclic    17
3    校驗矩陣查找表(Lookup Table)    23
4    LDPC解碼器架構    24
4.1    AROM模組    27
4.2    Bit Permutation模組    31
4.3    Intrinsic Information RAM模組    34
4.4    Barrel Shifter模組    36
4.5    Check Node Process模組    38
4.6    Rcv RAM模組    41
4.7    Rcv Decoder模組    43
4.8    Sv RAM模組    44
4.9    Parity Check模組    45
4.10    Adder模組    47
4.11    Subtractor模組    48
4.12    Accumulator模組    49
5    區塊式掃描動作流程    50
5.1    CNP模式    51
5.2    VNP模式    54
5.3    Data out模式    57
6    硬體環境    58
第四章、    硬體結果與效能    60
1    硬體調整    60
1.1    資料準確性(Check Node Process模組)    60
1.2    資料清空歸零(Sv RAM模組)    62
1.3    資料讀寫之地址(Sv RAM模組)    63
1.4    連續地址錯開排序(Sv RAM模組)    64
1.5    Parity Check機制(Parity Check模組)    65
1.6    資料做Hard decision處理    66
2    硬體資源使用率    67
3    硬體操作頻率    69
4    資料吞吐率    71
5    硬體驗證方式    74
6    硬體實現結果    76
6.1    解碼效能邊界(固定迭代次數、α與Scale)    76
6.2    Scale對解碼效能邊界的影響(固定迭代次數與α)    81
6.3    Bit Interleaver資料排序對解碼效能邊界的影響    82
6.4    BCH解碼器對解碼效能邊界的影響    83
第五章、    結論    84
參考文獻    85

                                

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