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研究生： 游理安
Li-An You
論文名稱： DVB-S2 LDPC 高資料率解碼器之FPGA 設計與實現
Design and Implementation of High Throughput DVB-S2 LDPC Decoder with FPGA
指導教授： 陳逸民
Yih-Min Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
論文出版年： 2022
畢業學年度： 110
語文別： 中文
論文頁數： 61
中文關鍵詞： 低密度奇偶檢查碼 、FPGA 、ZCU102 、第二代數位衛星通訊廣播 、軟體定義無線電 、解碼器 、QC-LDPC 、Min-Sum演算法
外文關鍵詞： LDPC code, FPGA, ZCU102, DVB-S2, Soft Defined Radio, Decoder, QC-LDPC Code, Min-Sum Algorithm
相關次數： 點閱：17  下載：0 
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    • 第二代數位衛星通訊廣播(DVB-S2)相較於DVB-S可提供更高的傳輸量，在通道編碼方面除使用LDPC code (Low-Dencity Parity-Check code)以及BCH code (Bose–Chaudhuri–Hocquenghem codes) 提供優異的錯誤更正能力，規格中亦支援多樣化的碼率及碼長以應付各式需求。
    本論文乃以ZCU102之FPGA硬體架構設計與實現完整DVB-S2中完整的LDPC Code 規格，其中包含各種碼率及碼長的LDPC Code。由於DVB-S2之LDPC校驗矩陣可經過重新排列的方式轉換成Quasi-Cyclic LDPC (QC-LDPC) Code校驗矩陣形式，此本論文之硬體架構包含掃描參數與控制模組、區塊迴旋移動模組、軟式輸入輸出 (soft input soft output, SISO) 解碼計算模組、解碼資訊更新模組。其中碼率與碼長的相關參數是以極特殊的資料結構儲存於記憶體並查表讀取，而SISO解碼演算法則利用Min-Sum演算法來降低硬體複雜度。本論文所實現之解碼器可由外部輸入參數配合控制訊號，使運行中的解碼器能即時切換後續輸入資料對應之LDPC Code 參數進行解碼。

    Second generation digital video satellite broadcasting(DVB-S2) is a new generation of digital satellite broadcasting standard specified for enhancing transmission capacity of the DVB-S. The main improvement of DVB-S2 relies on the new channel coding scheme which use LDPC(low-dansity-parity-check) code and BCH(Bose–Chaudhuri–Hocquenghem) code. And in the DVB-S2 specification, different code lengths and code rates are also provided, which can correspond to various needs.
    The research topic of this thesis is on the hardware architecture design and realization of the decoder for the complete DVB-S2 LDPC specification with ZCU102 FPGA evaluation board. Since all the parity matrices specified in the multi-rate DVB-S2 LDPC codes can be transformed in QC(quasi-cyclic)-LDPC codes particular reordering of data and parity-check, we uses a partial parallel and programmable hardware architecture, which is specially designed for QC-LDPC codes and based on a scanning scheme, as the hardware architecture of the decoder. The hardware architrcture includes parallel scanning parameters, control module, block circshift module, and soft input soft output decoding calculation module and decoding information update module. Among them, the related parameters of multi-bit rate and code length are stored in memory and the special data structure is completed in a look-up table mode. The SISO decoding algorithm uses the Min-Sum algorithm as the base to reduce the hardware complexity. The decoder implemented in this thesis can be achieved by external input parameters and control signals to change the corresponding DVB-S2 specification LDPC code rate and code length of the next set of incoming data during operation.

    摘要 iv Abstract v 誌謝 vii 目錄 viii 圖目錄 x 表目錄 xii 第一章 緒論 1 1-1 研究動機與背景 1 1-2 章節簡介 2 第二章 LDPC Code 3 2-1 LDPC Code之介紹 3 2-1-1 線性區塊碼(Linear block code) 3 2-1-2 Tanner Graph 4 2-2 LDPC Code之解碼演算碼 5 2-2-1 Sum-Product Algorithm 5 2-2-2 Normalized Min-Sum Algorithm 10 2-3 LDPC Code之編碼規格 12 2-3-1 Quasi-Cyclic 13 2-3-2 校驗矩陣查找表(Lookup Table) 16 第三章 FPGA實現LDPC解碼架構 18 3-1 FPGA開發環境 18 3-2 LDPC解碼器架構 19 3-2-1 Modified Min-Sum Algorithm[10] 21 3-2-2 區塊式掃描動作流程 22 3-2-3 Bit Permutation模組 27 3-2-4 AROM 模組 29 3-2-5 Intrinsic Infotmation RAM模組 33 3-2-6 Rcv RAM模組 34 3-2-7 Sv RAM模組 35 3-2-8 Barrel Sifter模組 35 3-2-9 Check Node Process模組 36 3-2-10 Rcv Decoder模組 38 3-2-11 Parity Check模組 38 第四章 系統硬體實現結果 40 4-1 硬體資源使用率 40 4-2 硬體測試結果與測試效能分析 43 4-3 降低處理速度硬體資源使用率 44 第五章 結論 46 參考文獻 47

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