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研究生: 曾益
Yi-Tseng
論文名稱: 應用深度學習於低軌衛星相控陣列之天線場型修復技術與晶片實現
Deep Learning-Based Antenna Pattern Recovery and Chip Implementation for Phased Array Systems in LEO Satellites
指導教授: 薛木添
Muh-Tian Shiue
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2025
畢業學年度: 114
語文別: 中文
論文頁數: 94
中文關鍵詞: 低軌衛星波束成型天線陣列天線失效旁瓣抑制深度神經網路
外文關鍵詞: LEO, Beamforming, Antenna array, Element failure, Sidelobe Level, Deep neural networks
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  • 本研究針對低軌道(Low Earth Orbit, LEO)衛星所使用之相控陣列天線系統進行探討,聚焦於天線單元失效所造成的波束品質劣化問題。由於衛星運行環境嚴苛,天線元件長期運作下容易因輻射、溫度循環或製程缺陷而產生故障,進而導致陣列輻射場型偏移,降低通訊效能。為解決此一挑戰,本研究提出一種基於深度學習之天線權重修復方法,透過輸入失效位置與原始權重配置,利用神經網路自動重新分配剩餘正常天線之權重,以實現容錯波束成形(fault-tolerant beamforming),有效恢復近似原始狀態之天線輻射模式。
    在演算法設計方面,本研究採用自編碼器(Autoencoder)神經網路架構,並透過大量模擬天線失效資料進行訓練,使模型能學習不同失效組合下的修復策略。模擬結果顯示,在單一、雙重與三重天線失效情境下,所提出方法皆能有效抑制旁瓣水準(SLL)並維持原始半功率波束寬度(HPBW),其平均修復率相較傳統啟發式演算法具有顯著提升。此外,本研究特別考慮天線失效位置之各種排列組合,不論位於中央或邊緣,皆能展現穩定修復效果,顯示其優異的泛化能力。
    本研究亦進一步將所提神經網路演算法實現為晶片架構,設計專用之運算單元、權重記憶體與近似激活函數電路,並透過Cell-based 流程於40 奈米CMOS 製程下完成電路實現,達成238 MHz 運作頻率,具備即時推論能力。研究成果驗證了深度學習結合硬體加速於衛星通訊應用的可行性,成功達成具備自我修復能力之衛星相控陣列系統設計目標。


    This study focuses on phased array antenna systems in Low Earth Orbit (LEO) satellites, addressing the beam quality degradation caused by antenna element failures. Due to the harsh space environment, antenna elements are prone to long-term faults from radiation, thermal cycling, or manufacturing defects, leading to deviations in radiation patterns and reduced communication performance. To tackle this challenge, we propose a deep learning–based antenna weight recovery method that reallocates the weights of functional elements based on failure locations and original configurations, thereby enabling fault-tolerant beamforming and restoring radiation patterns close to the original state.
    An Autoencoder neural network architecture is employed and trained with a large dataset of simulated antenna failures, enabling the model to learn recovery strategies under different fault combinations. Simulation results show that, for single, double, and triple element failures, the proposed method effectively suppresses sidelobe levels (SLL) and preserves the half-power beamwidth (HPBW), achieving significant improvements in average recovery rates compared with heuristic algorithms. Moreover, all possible failure position combinations are considered, and consistent recovery performance is achieved for both central and edge failures, demonstrating strong generalization capability.
    The algorithm is further implemented in hardware through a circuit architecture with dedicated computing units, weight memory, and approximate activation function circuits. Using a cell-based flow in a 40-nm CMOS process, the design achieves 238 MHz operating frequency with real-time inference capability. These results confirm the feasibility of combining deep learning with hardware acceleration for satellite communications and demonstrate the potential of self-healing phased array antenna systems.

    摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v 致謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi 目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x 表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 第一章緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 研究背景. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 論文貢獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 論文架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 第二章相位陣列天線系統介紹. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 相位陣列天線基本原理. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 陣列架構與分類. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 波束形成(Beamforming) 之數學建模與分析. . . . . . . . . . . . . . . . . 6 2.3.1 陣列因子(Array Factor) . . . . . . . . . . . . . . . . . . . . . . . 8 2.3.2 場型乘積原理. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.3 波束性能指標. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 權重設計策略概述. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 LEO 衛星於5G NR 系統中的波束管理機制. . . . . . . . . . . . . . . . . . 13 第三章天線故障對波束性能之影響分析. . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 元件故障模型(單一/多根天線失效) . . . . . . . . . . . . . . . . . . . . . 15 3.2 天線失效情況對場型圖性能之影響. . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 單一天線元素失效. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 多根天線元素失效. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 第四章基於Autoencoder 之稀疏權重修復模型設計與訓練流程. . . . . . . . . . 21 4.1 Autoencoder 架構原理與應用概述. . . . . . . . . . . . . . . . . . . . . . . 21 4.2 訓練資料生成與資料前處理. . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 損失函數(Loss Function) 設計. . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 激活函數(Activation Function) 介紹與選用. . . . . . . . . . . . . . . . . . 26 4.4.1 優化器(Optimizer)比較與選擇. . . . . . . . . . . . . . . . . . . 27 4.5 訓練參數設定與優化方法. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.5.1 超參數設定與搜尋空間. . . . . . . . . . . . . . . . . . . . . . . . . 32 4.5.2 貝葉斯最佳化方法(Bayesian Optimization) . . . . . . . . . . . . . 33 4.5.3 剪枝優化. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6 前向與反向傳遞機制之數學建模. . . . . . . . . . . . . . . . . . . . . . . . 40 第五章神經網路系統實現與模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 模型訓練架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 修復表現分類與量化. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 天線場型修復實驗結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4 與傳統方法之比較與分析. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 第六章硬體電路系統. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1 電路輸入及輸出. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 硬體系統架構方塊圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2.1 記憶體架構與資料存取流程. . . . . . . . . . . . . . . . . . . . . . 53 6.2.2 乘加處理單元(Processing Element,PE)設計. . . . . . . . . . . . 54 6.2.3 激活函數近似電路設計(Piecewise Linear Sigmoid) . . . . . . . . . 55 6.3 固定點數模擬與誤差分析. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4 有限狀態機控制電路與時序行為. . . . . . . . . . . . . . . . . . . . . . . . 59 第七章晶片設計結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.1 電路設計流程. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.2 電路模擬與驗證. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3 晶片佈局圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.4 錯誤覆蓋率. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.5 LVS 驗證結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.6 CHIP 總結與比較. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 第八章結論與未來展望. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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