跳到主要內容

簡易檢索 / 詳目顯示

回結果列表
研究生： 黃俊霖
Jun-lin Huang
論文名稱： 考慮線長匹配的平行匯流排之逃脫繞線
Escape routing for parallel buses considering length matching
指導教授： 陳泰蓁
Tai-chen Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 102
語文別： 中文
論文頁數： 50
中文關鍵詞： 繞線 、逃脫 、逃脫繞線 、線長 、匹配 、線長匹配 、平行匯流排 、匯流排 、平行
外文關鍵詞： escape, length-matching, parallel bus
相關次數： 點閱：18  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 隨著積體電路的快速發展，人們對於電路的要求逐漸提升，然而印刷電路板為了符合設計者的需求，繞線儼然已成為一個至關重要的議題。為了電路的信號穩定性與完整性，繞線處理的規格傾向於使用平行匯流排的觀念，要求等長、等距且盡可能地緊密匯合在一起。
    在眾多的印刷電路板繞線文獻當中，大部分都在區域繞線 (Area Routing) 階段作線長匹配的處理，鮮少有研究提早於逃脫繞線 (Escape Routing) 階段作此考量。我們提出了於逃脫繞線階段考量線長匹配問題的演算法，並且以平行匯流排的規格讓信號得以更優質的方式傳輸；此外，由於提早處理線長匹配問題，能有效地利用逃脫繞線階段的繞線資源，在區域繞線階段也可省去大量的面積，這將不同於一般的線長匹配考量僅為了滿足系統的時序設計而使用大量的蛇形走線 (Snaking)。
    實驗結果顯示，我們所提出的方法可以在極短的時間內達到百分之百的線長匹配，也可省去大量的區域繞線面積。

    As the integrated circuit advances, the circuit requirements by designers increase. In order to meet the needs of designers, the printed circuit board routing seems to be a critical issue. For signal stability and integrity of the routing, the concept of the parallel bus－including requirement of equal length, equidistance of nets and routing closely as possible－ is tend to be used as the specification of circuits.
    Among previous works for the printed circuit board routing, a majority of them considered length-matching issue in area routing stage. Hence, we proposed an algorithm which considers length-matching issue in an early stage, escape routing stage. With the use of the specification of a parallel bus, the routing allows better signal transmission. Furthermore, since we consider length-matching issue in advance, we can use the routing resources effectively in escape routing stage. Also, a lot of additional routing area can be avoided in area routing, and it decreases snaking routing significantly.
    As experimental results showed, our algorithm can save a lot of area in area routing, and achieve one-hundred-percent length matching within very short runtime.

    摘要 i Abstract ii 致謝 iii 目錄 iv 圖目錄 vii 表目錄 x 1 第一章、緒論 1 1-1 印刷電路板繞線 2 1-1-1 逃脫繞線 3 1-1-2 區域繞線 5 1-2 實際繞線情形 6 1-2-1 直角走線 6 1-2-2 蛇形走線 6 1-2-3 平行匯流排 7 1-3 相關研究 8 1-4 研究動機 9 1-5 問題定義與限制 10 1-6 論文結構 11 2 第二章、考慮線長匹配的平行匯流排之逃脫繞線 12 2-1 名詞解釋與定義 14 2-1-1 模型 14 2-1-2 起始點的挑選 15 2-1-3 叢集 (Clustering) 16 2-1-4 臨界路徑 (Critical Path) 17 2-2 選取臨界接腳 (Choose Critical Pin) 18 2-3 接腳叢集 （Cluster Pin） 20 2-4 臨界路徑繞線 （Route Critical Path） 21 2-5 分支路徑繞線 （Route Branch Path） 23 2-6 選擇最佳結果 （Choose The Best Result） 27 3 第三章、實驗數據 29 3-1 工作平台與測試檔說明 29 3-2 實驗結果 30 4 第四章、結論與未來展望 37 5 參考文獻 38

    [1] http://bookboon.com/en/introduction-to-electronic-engineering-ebook
    [2] T. Yan and M. D. F. Wong. “Correctly modeling the diagonal capacity in escape routing.” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 31, no. 2, pp. 285-293, Feb. 2012.
    [3] Q. Ma , T. Yan and M. D. F. Wong. "A negotiated congestion based router for simultaneous escape routing," Proc. Int. Symp. Qual. Electron. Des., pp.606 -610, Mar. 2010.
    [4] L. Luo , T. Yan , Q. Ma , M. D. F. Wong and T. Shibuya, "A new strategy for simultaneous escape based on boundary routing," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 2, pp.205 -214, Feb. 2011.
    [5] Hui Kong, Tan Yan and M. D. F. Wong, “Optimal simultaneous pin assignment and escape routing for dense PCBs,” In Proc. Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, pp. 275 - 280 Jan. 2010.
    [6] Sami Aarras, “Modern PCB design matching router technology with design challenges, ” ELKOM ECT FORUM, 2007.
    [7] M. M. Ozdal and M. D. F. Wong, “A length-matching routing algorithm for high-performance printed circuit boards,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 12, pp. 2784–2794, Dec. 2006.
    [8] T. Yan and M. D. F. Wong, “BSG-route: A length-matching router for general topology,” In Proc. Int. Conf. on Computer-Aided Design, pp. 499–505, Nov. 2008.
    [9] T. Yan and M. D. F. Wong, “BSG-Route: A length-constrainted routing scheme for general planar topology,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 28, no. 11, pp. 1679–1690, Nov. 2009.
    [10] T. Yan, P. C. Wu, Q. Ma, and M. D. F. Wong, "On the escape routing of differential pairs," in Proc. Int. Conf. on Computer-Aided Design, pp. 614-620, 2010.
    [11] Tai-Hung Li, Wan-Chun Chen, Xian-Ting Cai and Tai-Chen Chen, “Escape routing of differential pairs considering length matching,” In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 139 - 144, Feb. 2012.
    [12] K. Wang, H.X. Wang, and S.Q. Dong, “Escape routing of mixed-pattern signals based on staggered-pin-array PCBs,” In Proc. Int. Symp. on Physical Design., pp. 93-100, Mar. 2013.
    [13] Chung-Wei Yeh, “Simultaneous escape routing for mixed-pattern signals on staggered pin arrays,” National Central University Master Thesis, Aug. 2013.
    [14] Tan Yan, Hui Kong and M. D. F. Wong, “Optimal layer assignment for escape routing of buses,” in Proc. Int. Conf. on Computer-Aided Design, pp. 245 - 248, Nov. 2009.
    [15] Hui Kong, Tan Yan, M. D. F. Wong, and Ozdal, M.M. “Optimal bus sequencing for escape routing in dense PCBs,” in Proc. Int. Conf. on Computer-Aided Design, pp. 390 – 395, Nov. 2007.
    [16] Qiang Ma, Young, E.F.Y. and M. D. F. Wong, “An optimal algorithm for layer assignment of bus escape routing on PCBs,“ In Proc. Design Automation Conference (DAC), pp. 176 – 181, June. 2011.

    QR CODE
    :::