自旋力矩傳輸型磁阻式記憶體之高速電流模式感測放大器設計

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研究生：	城嘉聰 Chia-tsung Cheng
論文名稱：	自旋力矩傳輸型磁阻式記憶體之高速電流模式感測放大器設計 Design of the High Speed Current Mode Sense Amplifier for Spin Torque Transfer Magnetoresistive Random Access Memory
指導教授：	鄭國興 Kuo-hsing Cheng
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	98
語文別：	中文
論文頁數：	91
中文關鍵詞：	感測放大器、磁阻式記憶體
外文關鍵詞：	sensa amplifier, MRAM
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由於個人手持式終端產品日漸蓬勃發展，如行動電話、PDA、數位相機與iPod等通訊與消費性產品廣受消費者青睞，影音功能與資料處理運算能力不斷提升，故對記憶體之需求也越來越大。記憶體電路及其應用為提昇記憶體附加價值，並為未來晶片系統的關鍵技術。而嵌入式記憶體佔整個SoC的面積比例較以往大幅提升，顯示了嵌入式記憶體的重要性與日俱增。
本論文提出一個改良型的電流模式感測放大器，並搭配工研院的自旋力矩傳輸型磁阻式記憶體單元，設計出1Kb MRAM的記憶體電路。製程部分主要分為兩段，其前段製程是採用TSMC 0.18 μm 1P6M來實現，而後段製程則是採用ITRI EOL 65 nm搭配實現整體晶片，供應電源為1.8 V及2.5 V。其中，當MTJ在高阻態情況下的阻值為2132 Ω，而在低阻態情況下的阻值為1215 Ω及參考阻態阻值為1512 Ω。提出改良後的電流模式感測放大器可以有效地降低臨界電壓偏移量與提升在預充階段的充電速度，另外也達到降低輸入端偏壓流失率的效果，使感測電路不會因為輸入兩端偏壓值流失太快而影響到感測速度。
經模擬驗證，提出的感測放大器比一般的電流模式感測放大器在速度方面有較好的效能表現，且亦減少了功率延遲積（Power Delay Product ，PDP）的部分，另外也比較了自旋力矩傳輸型磁阻式記憶體單元在阻值上的偏移對感測放大器的影響。

According to the rapid evolution of hand-held products, the cell phone、PDA、digital camera and iPOD are more popular with people. The requirements of memory are more than before. The applications of memory circuits are the added value and the key technique for those components. Therefore, the embedded memory is more and more important in SoC.
A high-speed current mode sense amplifier for Spin Torque Transfer Magnetoresistive Random Access Memory (STT MRAM) is proposed. The circuit is fabricated by TSMC 0.18 μm 1P6M, the MTJ (Magnetic tunnel junction) utilizes ITRI EOL 65 nm process. The supply voltage are 1.8 V and 2.5 V. The resistance values of high state is 2132 Ω, low state is 1215 Ω, and reference state is 1512 Ω, respectively. The proposed sense amplifier decreases the dropping rate of input bias. In particular, it can reduce the sensing time and the power-delay-product (PDP).
The proposed sense amplifier has faster sensing delay than generally current mode sense amplifiers. The reductions of Power-Delay-Product (PDP) are also being. Furthermore, the proposed sense amplifier spends less sensing delay time under various resistances than the others.

摘要..................................................................................................................................I
ABSTRACT......................................................................................................................II
誌謝...............................................................................................................................III
目錄...............................................................................................................................IV
圖目錄............................................................................................................................VII
表目錄.............................................................................................................................XI
第1章 緒論......................................................................................................................1
1 研究背景................................................................................................................1
2 研究動機................................................................................................................2
3 論文組織................................................................................................................4
第2章 磁阻式記憶體基本概念.........................................................................................5
1 栓扣型磁阻式記憶體(TOGGLE MRAM)...................................................................5
2 自旋力矩傳輸型磁阻式記憶體 (SPIN TORQUE TRANSFER MRAM).....................8
2.1 自旋力矩與寫入翻轉....................................................................................8
2.2 讀取模式......................................................................................................8
2.3 Memory Cell.................................................................................................10
第3章 感測放大器.........................................................................................................15
1 電壓模式感測放大器(VOLTAGE MODE SENSE AMPLIFIER)......................................15
1.1 傳統差動感測放大器..................................................................................15
1.2 傳統正回授感測放大器..............................................................................20
2 電流模式感測放大器(CURRENT MODE SENSE AMPLIFIER)......................................24
2.1 電流模式之優點.........................................................................................24
2.2 Clamped Bit-Line Sense Amplifier.................................................................26
2.3 Chung’s Sense Amplifier................................................................................28
3 PROPOSED CURRENT MODE SENSE AMPLIFIER..........................................................31
3.1 感測放大器操作.........................................................................................31
3.2 模擬與比較.................................................................................................36
3.2.1 SA感測速度與輸出負載...............................................................................36
3.2.2 SA感測效能與功率延遲積(Power-Delay Product，PDP)..............................38
3.2.3 SA感測時間與MRAM阻值變動....................................................................41
第4章 1KBIT STT-MRAM設計.....................................................................................43
1 1K STT-MRAM電路架構......................................................................................43
2 設計流程..............................................................................................................45
3 電路元件詳圖......................................................................................................46
3.1 Row Decoder &Column Decoder...................................................................46
3.2 Tri-stage 三態閘..........................................................................................48
3.3 寫入電路....................................................................................................50
3.4 感測放大器與寫入電路..............................................................................54
3.5 3種 SA各1K MRAM之模擬結果.................................................................55
第5章 晶片佈局及量測..................................................................................................63
1 MRAM單元佈局...................................................................................................63
2 解碼器(DECODER)佈局.........................................................................................64
3 1KB磁阻式記憶體佈局.........................................................................................65
4 晶片佈局..............................................................................................................66
5 量測結果..............................................................................................................67
5.1 量測環境....................................................................................................67
5.2 感測放大器之量測結果..............................................................................69
第6章 結論....................................................................................................................74
參考文獻..........................................................................................................................75

                                

[1] http://www.mpsoc-forum.org/2004/slides/dks.pdf
[2] http://www.motorola.com/mot/doc/0/940_MotDoc.pdf
[3] http://nanodevice.kist.re.kr/Teams/nanodevice/mram.pdf
[4] W. Zhao, E. Belhaire, Q. Mistral, et al., “Macro-model of Spin-Transfer Torque based magnetic tunnel junction device for hybrid magnetic-CMOS design” IEEE International Behavioral Modeling and Simulation Workshop, Sept. 2006.
[5] T. Kawahara, R. Takemura, K. Miura, et al., “2 Mb SPRAM (SPin-Transfer Torque RAM) with Bit-by-Bit bi-Directional current write and parallelizing- direction current read”, IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 109-120, Jan. 2008.
[6] T. N. Blalock and R. C. Jaeger, “A High-Speed clamped bit-line current-mode sense amplifier,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp.542- 548, April. 1991.
[7] C. C. Chung, H. C. Lin and Y. T. Lin, “A novel high-speed sense amplifier for bi-NOR flash memories,” IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp.515-522, Feb.2005.
[8] H. S. Yu, J. C. Lim, S. W. Kim, et al., “Comparative study in response time between a current-mode and a voltage-mode sense amplifier for resistive loads in MRAM ”International Conference on Communications Circuits and Systems, pp 27-29 ,June 2004.
75
[9] T. P. Haraszti “CMOS Memory Circuits” United States of America: Kluwer Academic Publishers, 2002.
[10] J. J. Barnes and J. Y. Chan, “A High Performance Sense Amplifier for a 5V Dynamic RAM” IEEE Journal of Solid-State Circuits, vol. 15, no. 5, Oct.1980.
[11] T. P. Haraszti, “High Performance CMOS Sense Amplifier” United States Patent No.4, 169, 233,Sep. 1979.
[12] T. Seki, E. Itoh, C. Furukawa, et al., “A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier ” IEEE Journal of Solid-State Circuits, vol. 28, no. 4, April 1980.
[13] A. Hajimiri and R. Heald, “Design issues in cross-coupled inverter sense amplifier,” IEEE International Symposium on Circuits and Systems, vol. 2, no. 4, April 1980.
[14] E. Seevinck, P. J. Van Beers and H. Ontrop, “Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM’s,” IEEE Journal of Solid-State Circuits, vol. 26, no. 4, April 1991.
[15] S. E. Schuster and R. E. Matick, “Fast low power eDRAM hierarchical differential sense amplifier,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, Feb. 2009.
[16] W. Zhao, C. Chappert, V. Javerliac and J. P. Noziere, “High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits,” IEEE Transactions on Magnetics, vol. 45, no. 10, Oct. 2009.
[17] A. Conte, G. L. Giudice, G. Palumbo and A. Signorello, “A high-performance 76
very low-voltage current sense amplifier for nonvolatile memories,” IEEE Journal of Solid-State Circuits, vol. 40, no. 2, Feb. 2005.
[18] T. Kobayashi, K. Nogami, T. Shirotori and Y. Fujimoto, “A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE Journal of Solid-State Circuits, vol. 28, no. 4, April 1993.
[19] M. B. Leslie and R. J. Baker, “Noise-shaping sense amplifer for MRAM cross-point arrays,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, March 2006.
[20] Y. C. Lai and S. Y. Huang, “A resilient and power-efficient automatic-power-down sense amplifier for SRAM design,” IEEE Transactions on Circuits and Systems, vol. 55, no. 10, Oct. 2008.
[21] H. Zhang and P. Mazumder, “Design of a new sense amplifier flip-flop with improved power-delay-product,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1262-1265, May. 2005.
[22] S. Patil, M. Wieckowski and M. Margala, “A self-biased charge-transfer sense amplifier,” IEEE International Symposium on Circuits and Systems, pp. 3030-3033, May. 2007.
[23] R. Nebashi, N. Sakimura, H. Honjo, et al., “A 90nm 12ns 32Mb 2T1MTJ MRAM,” International Solid-State Circuits Dig. Tech. Papers, pp. 462-463,463a, Feb. 2009.
[24] M. Hosomi, H. Yamagishi, T. Yamamoto, et al., “A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram, ” International Electron
77
78
Devices Meeting Tech. Dig., pp. 459-462, 2005.
[25] T. Jiang and P. Y. Chiang, “Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing,” IEEE International Symposium on Circuits and Systems, pp. 181-184, May. 2009.
[26] J. Li, C. Augustine, S. Salahuddin and K. Roy, “Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement,” IEEE Design Automation Conference (DAC), pp. 278-283, 2008.

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