隨半導體產業發展與電腦相關產業的興起，資料傳輸頻寬逐漸上升，傳統並列傳輸方式漸漸被串列傳輸取代，例如DisplayPort、SATA、USB、及PCI-E等皆使用串列傳輸介面。本論文參考SATA 2/3規格實現一個時脈與資料回復電路，其中以鎖相迴路(Phase Lock Loop, PLL)為主體，並利用多頻帶閘控制電壓控制振盪器(Multi-band Gated-Voltage-Control-Oscillator, GVCO)實現兩種操作速率並降低電壓控制振盪器增益。
此論文使用TSMC 90 nm製程實現一個3/6 Gbps之雙速率時脈與資料回復電路(Clock and Data Recovery, CDR)，電路由四個部分所組成，分別是資料速率判斷電路、頻率資訊鎖相迴路、多頻帶閘控制電壓控制振盪器及時脈回復迴路。資料速率判斷用以偵測輸入資料的速率而調整電路頻寬與操作頻率；頻率資訊鎖相迴路可提供控制電壓與數位碼資訊供給多頻帶閘控制電壓控制振盪器對輸入資料進行解多工，將輸入資料速率降為原本的一半並且半速率(Half-rate)對齊輸入資料後再將對齊時脈送入時脈回復迴路；時脈回復迴路將還原出時脈以取樣輸入資料並還原資料。多頻帶閘控制電壓控制振盪器可實現兩種操作速率而避免使用多組不同振盪頻率之電壓控制振盪器，並且利用多頻帶之特性降低電壓控制振盪器增益，可降低電壓控制振盪器本身所造成的抖動。依據設計與模擬結果，抖動轉移函數頻寬為 2.1±1 MHz (SATA2)與4.2±2 MHz (SATA3)之間，在5 nH模擬打線電感之環境下，時脈峰對峰值抖動為28.3 ps(1.5 GHz) / 25.7 ps(3 GHz)，總面積為1252×1086 um2，電路核心面積580 416 um2，供應電源為1 V下，功率消耗為115 mW。

In recent year, according to rapid development of process and computers, the data bandwidth increases progressively. The serial data transmission is widely used for bus instead of parallel data transmission, for example, DisplayPort, SATA, USB, PCI-E. This study presents a clock and data recovery (CDR), and takes SATA 2/3 specification as reference material.
This study presents the CDR circuit fabricated in a 90-nm CMOS process and realizes a 3/6 Gbps dual-rate clock and data recovery. The CDR circuit consists of a frequency information phase-locked-loop, a data recovery loop, a multi-band gated-voltage-control-oscillator and a specification detector. The CDR employs a phase-lock-loop as the data recovery (DR) loop and the multi-band gated-voltage-control-oscillator which operates at dual frequency and reduces the voltage-control-oscillator gain. The specification detector detects the input data rate and modifies the operating frequency and bandwidth. The frequency information phase-locked-loop provides a analog voltage and digital codes to control the multi-band gated-voltage-control-oscillator which used to demux the input data into half-rate data streams. The data recovery loop recovers the recovered clock which samples input data and recovers data. The multi-band gated-voltage-control-oscillator operates at dual-rate without two oscillators and realizes the multi-band mechanism to reduce the jitter.
In terms of the CDR setting, conforming that the gain of error signal E(s) of -3 dB lies at the jitter frequency of 2.1±1 MHz (SATA2) and 4.2±2 MHz (SATA3). The 3/6 Gb/s input data is simulated with the 5 nH wire bonding and the peak-to-peak jitter of the recovered clock is 28.3 ps(1.5 GHz) / 25.7 ps(3 GHz). The whole chip area is 1252×1086 um2 and chip core area is 580 416 um2. The total power consumption is around 115 mW at supply voltage of 1 V.

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