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研究生： 黃俊豪
Jyun-Huo Haung
論文名稱： 基於鎖相迴路之多重相位脈波產生器
PLL Based Multi-Phases Clock Generator
指導教授： 鄭國興
Kuo-Hsing Cheng
周世傑
Shyh-Jye Jou
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 93
語文別： 英文
論文頁數： 102
中文關鍵詞： 鎖相迴路 、多重相位
外文關鍵詞： Phase-locked loop, multi-phases
相關次數： 點閱：7  下載：0 
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    • 晶片操作頻率及傳輸頻寬的增加引起了數兆赫時脈的龐大需求。然而單一時脈的頻率卻受限於信號反射、耦合以及供應電源的彈跳。因此多相位時脈技術被發展用來增進訊號的完整性及可靠度。它使用N個相位時脈取代單一的高頻時脈，而且能使頻率減少至單一時脈頻率的1/N。然而，多相位時脈的分佈卻是一個挑戰。時脈的繞線增加額外的面積和時序的不確定性。
    因此，我們提出一個創新的架構增進時序的效能以及減少繞線的面積。這個架構包含一個環形震盪器形式的鎖相迴路、相位打散器以及可調適四相位時脈信號產生器。雖然鎖相迴路的理論已經被深入發展，我們仍推導出實用的公式可以推算系統參數。多相位時脈由鎖相迴路產生而且靠著相位打散器傳遞，相位打散器被提出用來平均相位誤差。因為這個架構僅傳遞1/4數量的相位在時脈分佈上，繞線跟時脈信號緩衝器的功率消耗減少。
    最後，可調適四相位時脈信號產生器被用在廣域的次模組電路。這個電路由單一時脈再生四相位時脈，而且由於我們加入回授設計使這個電路增進了更廣的操作頻率範圍。兩個鎖相迴路已經以台積電0.18微米1P4M CMOS製程與聯電0.13微米1P8M CMOS製程實作，而在此發表的多相位分佈架構將以聯電0.13微米1P8M CMOS製程設計。

    Increases of chip operation frequency and transmission bandwidth result in a great demands for multi-GHz clocking. However the frequency of a single clocking is limited due to signal reflection, coupling, and supply bounce. Therefore, multi-phases clocking technique is developed to improve signal integrity and reliability. It uses N-phases clocking to replace single high frequency clocking, and can reduce frequency to 1/N of single clocking frequency. However, there is a challenge to the distribution of multi-phases clocking. The clocking routing increases the area overhead and timing uncertainty.
    Therefore, we propose a novel architecture to improve timing performance and reduce routing area. This architecture includes a ring-oscillator-based PLL, phase blenders, and adaptive quadrature clock generator. Although the PLL theory has been well developed, we derive practical and useful equations to estimate system parameters. The multi-phases clocking is generated by PLL and delivered by phase blenders, which has been proposed to average phase error. Because this architecture only delivers 1/4 numbers of phases on clock distribution, routing area and power consumption of clock buffers is decreased.
    Finally, the adaptive quadrature clock generators are employed in the global sub-module circuits. This circuit regenerates quadrature phases clocking from a single clocking and it has been improved to wider operation frequency range due to our feedback design. Two PLLs are implemented in tsmc 0.18μm 1P4M CMOS process and UMC 0.13μm 1P8M CMOS process, and the proposed multi-phases distribution architecture is designed in UMC 0.13μm 1P8M CMOS process.

    Chapter 1 Introduction 1 1.1 Thesis Motivation to Multi-phases Clocking Generator 1 1.2 Goal of This Thesis 2 1.3 Organization of This Thesis 4 Chapter 2 Priciples of Phase-Locked Loop 6 2.1 Introduction to PLL 6 2.1.1 Basic Operations in PLL 8 2.2 Brief History 9 2.3 PLL Architecture for Multi-phases Clocking 9 2.3.1 Phase / Frequency Detector and Charge Pump 11 2.3.2 Loop Filter 15 2.3.3 Voltage Controlled Oscillator and Interpolator 19 2.3.4 Divider 20 2.4 Analysis of PLL Linear Model 20 2.4.1 Performance in locked state 27 2.4.2 Acquisition 29 2.5 Performance Criteria and System Parameters 32 2.5.1 Loop bandwidth 33 2.5.2 Gain margin and phase margin 34 2.6 Summary 35 Chapter 3 Desing and Simulations of PLL 36 3.1 Behavioral Model Simulation 36 3.2 Circuit Implementation 45 3.2.1 Phase / Frequency Detector 46 3.2.2 Charge Pump 48 3.2.3 Loop Filter 50 3.2.4 Voltage Controlled Oscillator 50 3.2.5 Divider 57 3.3 Measurement Consideration 58 3.4 Simulations and Measurement Results 59 3.5 Noise and Jitter analysis 68 3.6 Summary 70 Chapter 4 Multi-phases Clock Generator Techique 71 4.1 Architecture of Multi-phases Clock Distribution 71 4.2 Quadrature Clock Generator 74 4.2.1 Interpolator 74 4.2.2 Duty Cycle Corrector 76 4.2.3 Adaptive Quadrature Clock Generator 78 4.3 Loop Analysis of Adaptive QCG 83 4.4 Summary 85 Chapter 5 Conclusions and Future Work 86 Bibliography 88 Appendix A. Formula Derivation 92 Appendix B. Architecture and Circuits of PLL-tsmc 93 Appendix C. Circuit Sizing of PLL 95 Appendix D. Simulation Results of QCG 98

    [1] R. E. Best, Phase-Locked Loops: Design. Simulation, and Applications, McGraw-ill Inc., 4th ed., 1999.
    [2] N.H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 2nd ed., 1993.
    [3] S.I. Ahmed, “Submicron CMOS Components for PLL-based frequency synthesis,” M.S. dissertation, Dept. of Electrical Engineering, N.E.D., Karachi, Pakistan, Aug. 2002.
    [4] M. Mansuri and C.K. K. Yang, “A Low-power Low-jitter Adaptive-bandwidth PLL and Clock buffer,” IEEE International Solid-State Circuits Conf., vol. 1, 2003, pp. 430–505.
    [5] J. Lin, B. Haroun, T. Foo, J.S. W., B. Helmick, S. Randall, T. Mayhugh, C. Barr and J. Kirkpatric, “A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process,” IEEE International Solid-State Circuits Conf., vol. 1, Feb. 2004, pp. 488-541.
    [6] C.C. Chen, “8 Gbps Serial Link Transmitter with Adaptive Termination and Pre-Emphasis,” M.S. dissertation, Dept. of Electrical Engineering, NCU, Taiwan, July 2004.
    [7] Y.Y. Wang, “Serial Link Receiver Design and Implementation,” M.S. dissertation, Dept. of Electrical Engineering, NCU, Taiwan, July 2004.
    [8] B. Razavi, “Monolithic Phase-Locked Loops and Clock Recovery Circuits-Theory and Design,” IEEE Press., 1996.
    [9] D. Mijuskovic, “Cell-Based Fully Integrated CMOS Frequency Synthesizers,” IEEE Journal of Solid-State Circuits, vol. 29, pp. 271-279, Mar. 1994.
    [10] C.L. Phillips and R.D. Harbor, Feedback Control Systems, Prentice Hall International Inc., 4th ed., 2000.
    [11] C.K. Yang and M.A. Horowitz, “A 0.8-μm CMOS 2.5Gb/s Oversampling Receiver and Transmitter for Serial Links,” IEEE Journal of Solid-State Circuits, vol. 31, pp.2015-2023, Dec. 1996.
    [12] C.K. K. Yang, Design of High-Speed Serial Links in CMOS, Sponscored by Center for Integrated Systems, Sun Microsystems, and LSI Logic Inc., 1998.
    [13] S.J. Jou, Digital Integrated Circuits and systems, Dept. of Electrical Engineering, NCU.
    [14] F. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. on Comm., vol. 28, pp. 1849-1858, Nov. 1980.
    [15] Brennan and V. Paul, Phase-Locked Loops: Principles and Practices, MacMillan Publishing, 1996.
    [16] D.K. Jeong, G. Borriello, D. A. Hodges and R.H. Katz, “Design of PLL-based clock generation circuits,” IEEE Journal of Solid-State Circuits, vol. 22, pp. 255-261, Apr. 1987.
    [17] P. Larsson, “Reduced pull-in time of phase-locked loops using a simple nonlinear phase detector,” IEE Proceedings Comm., vol. 132, Aug. 1995, pp. 221-226.
    [18] S.S. Sheu, “Design and Implementation of Low-Power and High-Noise-Immunity Phase-Locked Loop,” M.S. dissertation, Dept. of Electrical Engineering, Tamkang University, Taiwan, July 2002.
    [19] M. Perrott, “Design, Simulation, and Bandwidth Extension Methods for Fractional-N Frequency Synthesizers,” IEEE SSCS Taipei chapter short course, 2005.
    [20] S. Kim, K. Lee, Y. Moon, D.K. Jeong, Y. Choi and H.K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 691–700, May 1997.
    [21] I.A. Young, J.K. Greason, J.E. Smith and K.L. Wong, “A PLL clock generator with 5 to 110 MHz lock range for microprocessors,” IEEE International Solid-State Circuits Conf., Feb. 1992, pp. 50-51.
    [22] M.T. Wong, “A 2.5Gbps CMOS Serial Link Transceiver Design,” M.S. dissertation, Dept. of Electrical Engineering, NCU, Taiwan, June. 2002.
    [23] J.G. Maneatis and M.A. Horowitz, “Precise delay generation using coupled oscillators,” IEEE International Solid-State Circuits Conf., Dec. 1993, pp. 1273-1282.
    [24] J.G. Maneatis, J. Kim, I. McClatchie, J. Maxey, M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE Journal of Solid-State Circuits, vol. 38, p.p. 1795 – 1803, Nov. 2003, ISSCC., 2003.
    [25] J. G. Maneatis, “Low-jitter and process independent DLL and PLL based on self biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
    [26] A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacka and D. Stiurca, “A low jitter 125-1250 MHz process independent 0.18 μm CMOS PLL based on a sample-reset loop filter,” IEEE International Solid-State Circuits Conf., Feb. 2001, pp. 394-395.
    [27] V.V. Kaenel, D. Aebischer, Piguet C. and E. Dijkstra, “A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation,” IEEE International Solid-State Circuits Conf., Feb. 1996, pp. 132-133.
    [28] M. Mizuno, K. Furuta, T. Andoh, A. Tanabe, T. Tamura, H. Miyamoto, A. Furukawa and M. Yamashina, “A 0.18 μm CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator,” IEEE International Solid-State Circuits Conf., Feb. 1995, pp. 268-269.
    [29] S. Lizhong and D. Nelson, D, “A 1.0 V GHz range 0.13 μm CMOS frequency synthesizer,” IEEE Custom Integrated Circuits Conf., May. 2001, pp. 327-330.
    [30] S. Lizhong and Kwasniewski, “A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 910-960, June 2001.
    [31] G. Y. Wei, J. T. Stonick, D. Weinlader, J. Sonntag and S. Searles,” A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25um CMOS,” IEEE International Solid-State Circuits Conf., 2003.
    [32] F. Yang, J H. O''Neill and D. Inglis, “A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 1813-1821, Dec. 2001.
    [33] S. Williams, H. Thompson, M. Hufford and E. Naviasky, “An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter,” IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 151-154.
    [34] A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko and D. Stiurca, “Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs,” ISCAS, vol. 4, May 2001, pp. 766-769.
    [35] K.S. Chang, Advanced Analog Integrated Circuits, Dept. of Electrical Engineering, NCU.
    [36] K. Lim, S. Choi and B. Kim, “Optimal loop bandwidth design for low noise PLL applications,” Design Automation Conf., Jan. 1997, pp. 425-428.
    [37] K. Yamguchi, M. Fukaishi, T. Sakamoto, N. Akiyama and K. Nakamura, “2.5 GHz 4-phase clock generator with scalable and no feedback loop architecture,” IEEE International Solid-State Circuits Conf., Feb. 2001, pp. 398-399.
    [38] K. Nose and M. Mizuno, “Parallel clocking: a multi-phases clock-network for 10GHz SoC,” IEEE International Solid-State Circuits Conf., vol. 1, Feb. 2004, pp. 344-531.
    [39] N. Bindal, T. Kelly, N. Velastegui and K.L. Wong, “Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor,” IEEE International Solid-State Circuits Conf, vol. 1, 2003, pp. 346-498.
    [40] S.R. Han and S.I. Liu, “A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 463-468, Mar. 2004.
    [41] W.M. Lin and H.Y. Huang, “A low-jitter mutual-correlated pulsewidth control loop circuit,” IEEE Journal of Solid-State Circuits, vol. 39, pp. 1366-1369, Aug. 2004.
    [42] F. Mu and C. Svensson, “Pulsewidth control loop in high-speed CMOS clock buffers,” IEEE Journal of Solid-State Circuits, vol. 35, p.p. 134-141, Feb. 2000.
    [43] K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa and M. Yotsuyanagi, “A CMOS 50% duty cycle repeater using complementary phase blending,” Symposium on VLSI Circuits, June 2000, pp. 48-49.
    [44] J. Lee and B. Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1137-1145, Aug. 2000.

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