本論文的重點是使用文獻中所發表的記憶體式快速傅立葉轉換運算架構(Memory base FFT) 之分裂基數Split-radix 2/4，結合Hong所發表的普遍化不定資料分布存取方案 [19]，整合出適用於小至16點大到4096或8192點數的快速傅立葉轉換運算電路架構，並適用於無線通訊系統中的正交分頻多工 (OFDM) 多載波調變技術。
採用記憶體快速傅立葉運算架構比管線式快速傅立葉運算架構 (Pipeline base FFT)可節省電路面積、硬體成本、較高的蝴蝶運算單元硬體使用率和較低的存取功率消耗；而使用分裂基數 Split-radix 2/4 理論可減少蝴蝶運算單元 (Butterfly unit) 電路的複雜度，又可減少單一級數Pass運算時間，進而降低總運算時間；同時，記憶體存取方案 (Memory access scheme) 採用Hong所發表的普遍化不定資料分布存取方案，可固定蝴蝶運算單元架構，不需隨每一級數Pass做變動調整，僅需在蝴蝶運算單元和記憶體單位之間的資料交換存取控制電路做規律的邏輯排序。
綜合採取上述分別在演算法理論、運算架構複雜度、運算單元和記憶單元的硬體面積等優點，構思出本電路並實現，先後以 C++、MATLAB、Verilog HDL語言推導各種點數的正確性，最後再以 RTL Simulation、ISE 14.4進行模擬和合成 (Synthesis)，以及使用Xilinx Virtex 5 XC5VLX330 FPGA board進行驗證。

The focus of this thesis is to use the split-radix 2/4 published in the memory base fast Fourier transform (FFT) operation architecture. It combines with the generalized inconstant-distribution access scheme proposed by Hong to realize a circuit for the FFT operation ranging from as small as 16 points to as large as 4096 or 8192 points. In addition, it suits for orthogonal frequency division multiplexing (OFDM) multi-carrier modulation technology in wireless communication systems.
Comparing to pipeline-based FFT architecture, memory-based FFT architecture can obtain lower hardware cost, higher usage ratio of hardware in butterfly unit, and lower power consumption. While using split-radix 2/4 algorithm to reduce complexity of the butterfly unit circuit, the single-pass operation time can also be reduced, thereby reducing the total operation time. At the same time, the memory access scheme using the generalized inconstant- distribution access scheme proposed by Hong can have fixed butterfly operations. The butterfly unit structure does not have necessary to be adjusted with each Pass. It only needs to perform regular logical ordering on the data exchange access control circuit between the butterfly operation unit and the memory unit.
Based on the above-mentioned advantages of the algorithm, considering complexity of computing architecture, hardware area of computing unit and memory unit, etc., this circuit is conceived and implemented, and the verification of various FFT points is derived in C ++, MATLAB, Verilog HDL, and finally uses RTL Simulation, ISE 14.4 for behavior simulation and Circuit Synthesis, and Xilinx Virtex 5 XC5VLX330 FPGA board for evaluation.

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