在本篇論文中，我們提出一些應用於通訊系統中內嵌式數位信號處理器(Digital Signal Processor)之模組設計。 我們也提出一適用於此一內嵌式特性之輸入輸出(I/O)設計，此輸入輸出處理之資料包括程式碼及外部資料之輸入，其操作模式包含主機操作模式(Host Port Interface)、平行操作模式(Parallel)及即時資料操作模式(Real time)。
在資料通路(Data path)上，我們也提供 40 位元之算數邏輯運算單元及具有左移15右移16位之位移器和有限脈衝頻率響應(Finite Impulse Response, FIR)。 除此之外我們也提供一些另外的選擇，如通訊上常用之特殊運算單元如Hamming 距離之計算及多層切片器(Slicer) ，以上所提之法雖可用軟體方法實現但在系統速度要求越來越高之時會有不敷使用之憾，所以提供特殊應用指令之硬體實現之模組實為未來高速DSP之趨勢。 在FIR 的應用中我們亦提出一可縮減位元長度式乘法器，此一概念應用在陣列式乘法器上可有效降低面積48%，並拓展此法至Booth乘法器之加法列，其訊雜比(SNR)亦比多取一位元之加法列高出3dB而且面積省了10%。
最後，本篇論文亦提供模組設計流程其中包括: ALU，位移器，Slicer 及Hamming 距離計算器。 而且這些模組產生器所產生之Verilog皆為可被合成之程式碼。

In this thesis, the some modules used in the programmable DSP embedded core for communication system are proposed. The proposed I/O function combines the data and program source that include Host-Port-Interface (HPI), parallel and Real-time mode. In the data-path of our DSP, we develop the 40-bits ALU and 40-bits Barrel-shifter with shift +15 to -16. Besides, we also provide the optional hardware functions. Such as Hamming-Distance-Calculator, Multi-Level-Slicer and FIR filter. The Hamming-Distance-Calculator can calculate the minimum distance of two 16-bits input data in 5.22 ns. In some communication application, we usually need the variable slicer-level to help the system increase the performance. About the optional FIR function, we will propose a new reduced-width multiplier that can replace the multiplier in conventional filter and save 48% area in each multiplier of the FIR filter.
In this thesis, we also provide module generator for ALU, Barrel-shifter Multi-Level-Slicer and Hamming-Distance-Calculator and these generators generate the synthesizable Verilog code.

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