利用等效電路模型來改善二維與三維半導體元件模擬之效率

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研究生：	張家誠 Chia-Cherng Chang
論文名稱：	利用等效電路模型來改善二維與三維半導體元件模擬之效率 Improvement of 2-D and 3-D Semiconductor Device Simulation Using Equivalent-circuit Model
指導教授：	蔡曜聰 Yao-Tsung Tsai
口試委員:
學位類別：	博士 Doctor
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	94
語文別：	英文
論文頁數：	118
中文關鍵詞：	動態臨界電壓金氧半電晶體、絕緣體上矽、負微分電阻振盪器、平帶電壓、水平積分、準三維元件模擬器、元件分割法、小電阻連線法
外文關鍵詞：	horizontal integration, small-resistance coupling, NDR oscillator, SOI, DTMOS, quasi-3D simulator, device partition method, flat-band voltage
相關次數：	點閱：16 下載：0
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近年來，半導體製程技術快速的發展。在半導體產業裡，元件特性的模擬經常被使用來降低製造的成本與時間。因此開發半導體元件模擬器就變成相當重要的任務。然而在二維或三維元件的數值模擬分析裡，是需要消耗大量的記憶體空間和電腦計算時間。因此在本論文中，我們提出了元件分割法(device partition method)、小電阻連線法(small-resistance coupling)及準三維的元件模擬技術來改善我們現有的元件與電路混階模擬器的效率。在元件分割法的研究方面，我們已經展示出元件模擬所需的記憶體空間會隨著元件分割數目的增加而降低。在電腦計算時間的改善方面，我們在三維的元件模擬裡也觀察到電腦計算時間會隨著元件分割數目的增加而降低。另外，在元件與電路混階模擬研究方面，我們已經提出了小電阻連線法來改善過去無法以帶狀形矩陣(band matrix)解法器來探討外部連線較複雜的元件與電路模擬。在本論文裡，我們也使用小電阻連線法來探討負微分電阻、石英晶體及環狀型振盪器等電路。在準三維的元件模擬研究方面，因為主要載子的準費米能階(quasi-Fermi level)幾乎為水平，所以外部的電壓源可以直接加在主要載子的電路上且可得到一近似以傳統三維元件模擬器計算的解。在應用方面，我們也以此準三維元件模擬的技術來探討body-tied結構的SOI MOSFET和動態式臨界電壓的(dynamic threshold voltage) MOSFET。最後，我們分別以垂直積分法和水平積分法的等效電路模型來探討非理想的金氧半電容的平帶電壓(flat-band voltage)。

In the recent years, the semiconductor manufacturing technology proceeded at a very rapid pace. The simulation of device’s characteristic is always used to reduce the manufacturing cost and time in the semiconductor industry. Therefore, it is a very important task to develop the device simulation. However, it requires a considerably huge amount of memory size and calculation time in 2-D or 3-D device simulation. Therefore, we propose the device partition method (DPM), small-resistance coupling (SRC) method, and quasi-3D technique to improve our mixed-level device and circuit simulator in this dissertation. In DPM, we have demonstrated that the lower consumption of memory accompanies the larger part number of DPM in 2-D or 3-D device simulation. Besides, we have also demonstrated that the calculation time decreases as the part number of DPM increases in 3-D device simulation. Furthermore, we have proposed SRC method to improve the limit on the discussion of the complicated mixed-level device and circuit simulation using the band matrix solver. In this dissertation, we also use SRC method to study the negative-differential-resistance oscillator, crystal oscillator, and CMOS ring oscillator circuits. In the quasi-3D device simulation, because the quasi-Fermi level of majority carrier is nearly constant, the voltage source can be connected to the majority carrier circuit. Therefore, we can obtain the solution that is close to the conventional 3-D device simulator. In the application of quasi 3-D device simulation, we also use the quasi-3D technique to study the body-tied SOI MOSFET and dynamic threshold voltage MOSFET (DTMOS). Finally, we use the equivalent circuit models for the vertical and horizontal integrations to study the flat-band voltage of non-ideal MOS-C.

Chapter 1. Introduction                                                       1
Chapter 2. Overview of Numerical Device Simulation                            5
2.1 Discretization of Semiconductor Equations                                5
2.2 The Matrix Solvers and Variable Permutation Methods                      9
2.2.1 Band Matrix Solver                                                   9
2.2.2 Levelized Incomplete LU Method                                      14
2.3 2-D and 3-D Equivalent Circuit Models                                   17
Chapter 3. Device Partition Method in Device Simulation                      24
3.1 Device Partition Method in 2-D Device Simulation                        25
3.1.1 Two-part DPM                                                        26
3.1.2 Three-part and Four-part DPMs                                       29
3.1.3 Two-dimensional MOSFET Simulation                                   33
3.1.4 CMOS Inverter Simulation                                            35
3.2 Device Partition Method in 3-D Device Simulation                        38
3.2.1 Principle and Modeling for the 3-D DPM                              39
3.2.2 3-D PN Diode Simulation                                             43
3.2.3 3-D MOSFET Simulation                                               45
3.3 Discussion of the Simulation Efficiency in DPM                          47
Chapter 4. Two-dimensional Mixed-level Device and Circuit Simulation using
Band Matrix Solver                                                53
4.1 Small-resistance Coupling Method in Band Matrix Solver                  54
4.2 Negative-differential-resistance Oscillator                             56
4.3 Crystal Oscillator                                                      60
4.4 CMOS Ring Oscillator                                                    63
Chapter 5. Quasi-3-D Device Simulation for SOI MOSFET                        68
5.1 Silicon-On-Insulator (SOI) MOSFET                                       69
5.1.1 Partially Depleted and Fully Depleted                               69
5.1.2 Floating Body Effect                                                71
5.1.3 Impact Ionization Model                                             75
5.2 The Body-tied SOI MOSFET Simulation                                     79
5.3 Dynamic Threshold Voltage MOSFET Simulation                             83
Chapter 6. Understanding the Superposition of MOS Flat-band Voltage with
Horizontal Integration                                            89
6.1 Introduction                                                            90
6.2 The Equivalent-circuit Modeling for the Vertical and Horizontal
Integrations                                                            96
6.3 Simulation results and comparison                                      100
Chapter 7. Conclusion                                                       107
References                                                                  110
Biography                                                                   116
Publication List                                                            117

                                

[1] H. K. Gummel, “A self-consistent iterative scheme for one-dimensional steady state transistor calculations”, IEEE Trans. Electron Devices, pp.455-465, 1964.
[2] C. C. Chang, J. F. Dai, F. W. Lin, S. J. Li, and Y. T. Tsai, “Device-Partition Method in Two-Dimensional Device Simulation,” ICICS2003, Kaohsiung, Taiwan, 2003.
[3] C. C. Chang, S. J. Li, and Y. T. Tsai, “Device-partition method using Equivalent Circuit Model in Two-dimensional Device Simulation,” International Journal of Numerical Modelling, vol. 18, pp. 203- 219, 2005.
[4] C. C. Chang, S. J. Li, and Y. T. Tsai, “Device-Partition Method Using Equivalent Circuit Method in Three-Dimensional Device Simulation,” in EDMS 2005, Kaohsiung, Taiwan, 2005.
[5] C. C. Chang, S. J. Li, and Y. T. Tsai, “Two-dimensional Mixed-level Device and Circuit Simulation using a simple Band Matrix Solver,” in EDMS 2005, Kaohsiung, Taiwan, 2005.
[6] J. Vlach, Computer Methods for Circuit Analysis and Design, Chapter 2, Van Nostrand Reinhold, 1994.
[7] C. Y. Lee, “Levelized Incomplete LU Factorization and Its Application to Semiconductor Devices,” M. S. thesis, National Central University, Taiwan.
[8] M. K. Tsai, “An Improve Levelized Incomplete LU Method and Its Application to 2D Semiconductor Devices Simulation,” M. S. thesis, National Central University, Taiwan.
[9] J. F. Dai, “Development of 2-D and 3-D Numerical Device Simulator including an Improved L-ILU Solver and the Circuit representation of PDM,” Ph.D. dissertation, National Central University, Taiwan.
[10] A. R. Brown, A. Asenov, S. Roy, and J. R. Barker, “Development of a Parallel 3D Finite Element Power Semiconductor Device Simulator,” Physical Modelling of Semiconductor Devices, IEE Colloquium on, Page(s): 2/1 -2/6, 1995.
[11] T. F. Pena, E. L. Zapata, and D. J. Evans, “Finite Element Simulation of Semiconductor Devices on Multiprocessor Computers,” Parallel Computing, 20, pp. 1129-1159, 1994.
[12] Y. T. Tsai, and T. C. Ke “Electrode Separation Method to the Boundary Condition for a-Si TFT Mixed-level Simulation.” International Journal of Numerical Modelling: Electronic Networks, Devices, and Fields, vol.11, pp. 123-130, 1998.
[13] Y. T. Tsai, C. Y. Lee, and M. K. Tsai “Levelized incomplete LU method and its application to semiconductor device simulation,” Solid-state Electronics, Vol. 44, pp. 1069-1075, 2000.
[14] Y. T. Tsai, C. F. Dai and M. K. Tsai, “ An Improved Levelized Incomplete LU Method And Its Application to 2D Semiconductor Device Simulation,” Journal of Chinese Institute of Engineers, vol.24, pp.389-396, 2001.
[15] L. W. Nagel, “SPICE2: A computer to simulate semiconductor circuit”, Univ. California Berkeley, ERL Memo ERL-M520, May 1975.
[16] Medici 2000.4 User’s Manual. Avant! Corporation, 2000
[17] C. C. Chang, J. F. Dai, Y. M. Sun, and Y. T. Tsai “Levelized Incomplete LU Factorization and its Application to Quasi-static MOSFET C-V Simulation.” Journal of the Chinese Institute of Electrical Engineering, Vol. 10, pp. 117-123, 2003.
[18] H. C. Casey, jr., Devices for Integrated Circuits, Silicon and III-V Compound Semiconductors, Chapter 8, John Wiley & Sons, Inc., 1999.
[19] N. Shigyo, M. Konaka, and R. L. M. Dang, “Three-Dimensional simulation of inverse narrow-channel effect,” Electron. Lett., vol. 18, pp. 274-275, 1982.
[20] H. Chan and T. Shieh, “A three-dimensional semiconductor device simulator for GaAs/AlGaAs heterojunction bipolar transistor analysis,” IEEE Trans. Electron Devices, vol. 38, pp. 2427-2432, Nov. 1991.
[21] K. Varahramyan, S. Arshad, W. P. Masazara, “Three-Dimensional modeling and evaluation of body tied versus floating body SOI MOSFETs,” Microelectronic Engineering, vol. 45, pp. 29-37, 1999.
[22] J. Colinge, “Multiple-gate SOI MOSFETs,” Solid-state Electronics, vol. 48, pp.897-905, 2004.
[23] J. G. Rollins and J. Choma, “Mixed-mode PISCES-SPICE coupled circuit and device solver, “ IEEE Transactions on computer-aided design, vol. 7, pp. 862-867, Aug. 1988.
[24] K. Mayaram and D. O. Pederson, “CODECS: A Mixed-level Device and Circuit Simulation,” in Proc. IEEE Int. Conf. Computer-aided Design, pp. 813-820, Nov. 1987.
[25] K. Mayaram and D. O. Pederson, “Coupling Algorithms for Mixed-level Circuit and Device Simulation,” IEEE Transactions on computer-aided design, vol. 11, no. 8, pp. 1003-1010, 1992.
[26] K. Mayaram, J. H. Chern, and P. Yang, “Algorithms for Transient Three-Dimensional Mixed-Level Circuit and Device Simulation,“ IEEE Transactions on computer-aided design, vol. 12, no. 11, pp. 1726-1733, 1992.
[27] T. Grasser and S. Selberherr, “Mixed-mode device simulation, “ Microelectronics Journal, vol. 31, pp. 873-881, 2000.
[28] C. C. Chang, J. F. Dai, and Y. T. Tsai, “Verification of 1D BJT numerical simulation and its application to mixed-level device and circuit simulation, “ International Journal of Numerical modeling: Electronic Networks, Devices, and Fields, vol. 16, pp. 81-94, 2003.
[29] J. F. Dai, C. C. Chang, and Y. T. Tsai, “ Further improvements in equivalent-circuit model with levelized incomplete LU factorization for mixed-level semiconductor device and circuit simulation, “Solid-state Electronics, vol. 48, pp.1181-1188, 2004.
[30] J. F. Dai, C. C. Chang, J. W. Lee, S. J. Li, and Y. T. Tsai, “Simplified equivalent-circuit modeling for decoupled and partial decoupled methods in semiconductor device simulation, “International Journal of Numerical modeling: Electronic Networks, Devices, and Fields, vol. 17, pp. 421-432, 2004.
[31] W. L. Engl, R. Laur, and H. K. Dirks, “MEDUSA - A simulator for modular circuits, “IEEE Transactions on computer-aided design, vol. 1, pp.85-93, Apr. 1982.
[32] C. K. Alexander, and M. N. O. Sadiku, Fundamentals of Electric Circuits, Chapter 8, McGRAW-Hill, 2000.
[33] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Chapter 12, Saunders College Publishing, 1991.
[34] J. M. Rabaey, Digital Integrated Circuits, Chapter 3, Prentice Hall, 1996.
[35] S. M. Kang, Y. Leblebici, CMOS Digital Integrated Circuit: Analysis And Design, Chapter 6, McGRAW-Hill, 1996.
[36] S. Maeda, Y. Yamaguchi, I. J. Kim, T. Iwamatsu, T. Ipposhi, S. Miyamoto, S. Maegawa, K. Ueda, K. Mashiko, Y. Inoue, T. Nishimura, and H. Miyoshi, “Analysis of delay time instability according to the operating frequency in field shield isolated SOI circuits, ” IEEE Trans. Electron Devices, vol. 45, pp.1479-1486, 1998.
[37] S. Maeda, Y. Hirano, Y. Yamaguchi, T. Iwamatsu, T. Ipposhi, K. Ueda, K. Mashiko, S. Maegawa, H. Abe, and T. Nishimura, “ Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp.151-158, 1999.
[38] T. Iwamatsu, Y. Yamaguchi, Y. Inoue, T. Nishimura, and N. Tsubouchi, “CAD-compatible high-speed CMOS/SIMOX gate array using field- shield isolation, “ IEEE Trans. Electron Devices, vol. 42, pp.1934-1939, 1995.
[39] T. Iwamatsu, Y. Yamaguchi, K. Ueda, K. Mashiko, Y. Inoue, and T. Hirao, “High-speed 0.5 mm SOI 1/8 frequency divider with body-fixed structure for wide range of applications,” in Ext. Abst. SSDM, PP.575, 1995.
[40] W. Chen, Y. Taur, D. Sadana, K. A. Jenkins, J. Sun, and S. Cohen, “Suppression of the SOI floating-body effects by linked-body device structure,” in Symp. VLSI Tech., pp. 92, 1996.
[41] K. Kato, T. Wada, and K. Taniguchi, “Analysis of kink characteristics in silicon-on-insulator MOSFET’s using two-carrier modeling,” IEEE Trans. on Electron Devices, vol. 32, pp.458-462, 1985.
[42] S. P. Edwards, K. J. Yallup, and K. M. D. Meyer, “ Two-dimensional numerical analysis of the floating region in SOI MOSFET’s,” IEEE Trans. on Electron Devices, vol. 35, pp.1012-1020, 1988.
[43] K. K. Young and J. A. Burns, “ Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFET’s,” IEEE Trans. on Electron Devices, vol. 35, pp.426-431, 1988.
[44] M. Yoshimi, M. Takahashi, T. Wada, K. Kato, S. Kambayashi, M. Kemmochi, and K. Natori, “ Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET’s,” IEEE Trans. on Electron Devices, vol. 37, pp.2015-2021, 1990.
[45] J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F Hemment, “ Improved subthreshold characteristics of n-channel SOI transistors,” IEEE Electron Device letters, vol. 7, pp.570-572, 1986.
[46] J. G. Fossum, R. Sundaresan, and M. Matloubian, “ Anomalous subtreshold current-voltage characteristics of n-channel SOI MOSFET’s,” IEEE Electron Device letters, vol. 8, pp.544-546, 1987.
[47] M. Terauchi, M. Yoshimi, A. Murakoshi, and Y. Ushiku, “Supression of the floating-body effects in SOI MOSFETs by bandgap engineering,” in VLSI Sym. Dig. Tech. Papers, pp.35-36, 1995.
[48] J. P. Colinge, “ Silicon-on-insulator technology: materials to VLSI, ” Chapter 5, Kluwer Academic Publishers, 2004
[49] J. Tihani and H. Schlotterer, “Properties of ESFI MOS transistors due to the floating substrate and the finite volume,” IEEE Trans. on Electron Devices, vol. 22, pp. 1017-1023, 1975.
[50] J. Colinge, “Reduction of kink effect in thin-film SOI MOSFET’s,” IEEE Electron Device Letters, vol. 9, pp. 97-99, 1988.
[51] J. B. Kuo and S. C. Lin, “Low-voltage SOI CMOS VLSI devices and circuits,” Chapter 2, John Wiley & Sons, Inc., 2001.
[52] G. G. Shahidi, “SOI technology for the GHz era,” IBM J. RES. and DEV., vol. 46, pp.121-131, 2002.
[53] M. Matloubian, C.E.D. Chen, B.Y. Mao, R. Sundaresan, G. P. Pollack, “Modeling of the subthreshold characteristics of SOI MOSFET’s with floating body,” IEEE Trans. on Electron Devices, vol. 37, pp. 1985-1994, 1990.
[54] A. Schutz, S. Selberherr, and H. W. Potzl, “ A two-dimensional model of the avalanche effect in MOS transistors,” Solid-state Electronics, vol. 25, pp.177-183, 1982.
[55] A. Schutz, S. Selberherr, and H. W. Potzl, “ Analysis of breakdown phenomena in MOSFET’s,” IEEE Trans. on CAD, vol.1, pp.77-85, 1982.
[56] S. E. Laux and B. M. Grossman, “ A general control-volume formulation for modeling impact ionization in semiconductor transport,” IEEE Trans. on. Electron Devices, vol. 32, pp. 2076-2082, 1985.
[57] S. Selberherr, “Analysis and simulation of semiconductor devices,” Springer-Verlag, 1984.
[58] S. J. Li, “An Equivalent Circuit of Impact-Ionization and its Applications on Semiconductor Devices,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2002.
[59] L. L. Liou and C. I. Huang, “Using constant base current at a boundary condition for one-dimensional AlGaAs/GaAs numerical heterojunction bipolar transistor simulation,” Electronics Letters, vol. 26, pp. 1501-1503, 1990.
[60] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “ A dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage operation,” in IEDM Tech. Dig., pp.809-812, 1994.
[61] F. Assaderaghi, S. A. Parke, D. Sinitsky, J. Bokor, P. K. Ko, and C. Hu, “ A dynamic threshold-voltage MOSFET (DTMOS) for very low voltage operation,” IEEE Electron Device Letters, vol. 15, pp.510-512, 1994.
[62] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “ Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans. on Electron Devices, vol. 44, pp.414-422, 1997.
[63] B. E. Deal, “Standardized Terminology for Oxide Charges Associated with Thermally Oxidized Silicon,” IEEE Trans. on Electron Device, vol. 27, p.606, 1980.
[64] S. Wolf, Silicon processing for the VLSI era volume 3, Chapter 3, Lattice press, 1995.
[65] H. C. Casey, jr., Devices for Integrated Circuits, Silicon and III-V Compound Semiconductors, Chapter 7, John Wiley & Sons, Inc., 1999.
[66] J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology- Fundamentals, Practice and Modeling, Chapter 2, 2000.
[67] C. C. Chang, S. J. Li, and Y. T. Tsai, “An Equivalent-circuit Modeling on Vertical and Horizontal Integrations for MOS Flat-band Voltage Simulation,” International Journal of Numerical Modelling , vol. 19, pp. 289- 300, 2006.

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