本論文主旨在開發並優化應用於絕緣層上矽（SOI）基板之環繞式閘極電晶體（GAAFET）的蝕刻製程，並藉由嚴謹的電性與材料分析技術，驗證其在次世代半導體元件中的應用潛力。隨著半導體製程演進至3奈米節點以下，GAAFET以其卓越的靜電控制能力，成為接替鰭式場效電晶體（FinFET）的關鍵架構。本研究使用感應耦合式電漿（ICP）蝕刻系統，以HBr/Cl₂/SF₆氣體化學為基礎，系統性地探討蝕刻參數對製作懸浮式鍺（Ge）通道的影響，目標為建立一套穩定且高效能的奈米級元件製造方案。

本研究之量測與分析方法涵蓋多個層面：首先，利用掃描式電子顯微鏡（SEM）進行橫截面觀察，以評估懸浮式奈米通道的幾何形貌、側壁垂直度與結構完整性，並檢視其與SOI基板的界面品質。其次，透過電流-電壓（I-V）特性量測，深入探討閘極堆疊品質與元件的開關特性，包括臨界電壓（V th ）、開關電流比（I on/I off ）與次臨界擺幅（S.S.），並以此評估元件的等效氧化層厚度（EOT）與界面陷阱密度，全面地分析製程優化對電性表現的實質貢獻。

實驗結果顯示，透過對射頻偏壓與HBr氣體比例的精準調控，成功實現了蝕刻非等向性（Anisotropy）達0.91的垂直通道輪廓。基於此優化製程所製作的N型GAAFET元件，展現了優異的開關特性，其開關比超過 10^4，次臨界擺幅則低至107 mV/dec。GAAFET結合SOI基板的架構，不僅具備最極致的靜電控制能力以抑制短通道效應，更能有效降低寄生電容與功耗。未來GAAFET元件的發展將朝向多層奈米片堆疊、更先進的通道材料與3D系統整合方向演進，本研究為此發展趨勢提供了關鍵的蝕刻製程基礎與驗證，展現了其在未來高效能運算與低功耗應用中的巨大潛力。

This paper focuses on the development and optimization of the etching process for Gate-All-Around Field-Effect Transistors (GAAFETs) on Silicon-on-Insulator (SOI) substrates, aiming to validate their potential for next-generation semiconductor devices through rigorous electrical and material analysis. As semiconductor manufacturing progresses beyond the 3 nm node, GAAFETs have emerged as a critical architecture to succeed Fin Field-Effect Transistors (FinFETs) due to their superior electrostatic control. This study utilizes an Inductively Coupled Plasma (ICP) etching system, employing HBr/Cl₂/SF₆ gas chemistry, to systematically investigate the influence of etching parameters on the fabrication of suspended Germanium (Ge) channels, with the objective of establishing a stable and high-performance nanoscale device manufacturing solution. The measurement and analysis methods in this study encompass several aspects: first, cross-sectional scanning electron microscopy (SEM) is employed to evaluate the geometrical morphology, sidewall verticality, and structural integrity of the suspended nanowire channels, along with examining their interface quality with the SOI substrate; second, current-voltage (I-V) characteristic measurements are conducted to thoroughly investigate the gate stack quality and the switching characteristics of the device, including threshold voltage (Vth), on/off current ratio (Ion/Ioff), and subthreshold swing (S.S.), which are then used to assess the device's equivalent oxide thickness (EOT) and interface trap density, providing a comprehensive analysis of the substantive contribution of process optimization to electrical performance. Experimental results demonstrate that precise control over radio frequency (RF) bias and HBr gas ratio successfully achieved a vertical channel profile with an etching anisotropy of 0.91. The n-type GAAFET devices fabricated using this optimized process exhibit excellent switching characteristics, with an on/off current ratio exceeding 104 and a subthreshold swing as low as 107 mV/dec. The GAAFET architecture, combined with SOI substrates, not only offers ultimate electrostatic control to effectively suppress short-channel effects but also significantly reduces parasitic capacitance and power consumption. This research provides a crucial foundation and validation for the etching process, supporting future trends in GAAFET device development, including multi-nanosheet stacking, more advanced channel materials, and 3D system integration, highlighting the immense potential of this technology for future high-performance computing and low-power applications.

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