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研究生： 歐亭鎔
Ting-rong Ou
論文名稱： 利用平行處理架構之 CRC 網路封包錯誤更正器研製
The Design and Implementation of CRC Based Packet ErrorCorrector Using Parallel Architecture
指導教授： 許獻聰
Shiann-tsong Sheu
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 通訊工程學系
Department of Communication Engineering
畢業學年度： 98
語文別： 英文
論文頁數： 74
中文關鍵詞： 封包錯誤更正
外文關鍵詞： CRC
相關次數： 點閱：14  下載：0 
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    • 現今的網路模型中的媒體存取控制（Medium Access Control - MAC）層使用
    CRC-32 的編碼方式，先對原始資料進行編碼之後封裝為資料訊框再進行傳輸。當
    接收端收到資料訊框後，會計算此訊框的 CRC-32 餘數以檢查所接收到的訊框是否
    正確。如果 CRC-32 檢測訊框有錯誤，接收端的 MAC 層會使用 ARQ（Automatic
    Repeat reQuest）協定進行訊框的重傳，以期待再次的重傳可以收到正確的訊框。
    ARQ 詳細的運作機制如下，當傳送端送出訊框後，會等待接收端對這個訊框回應
    一個「確認收到(acknowledge, ACK)」的訊息。如果經過一段時間傳送端沒有收到
    ACK（稱之為 timeout），很可能接收端沒有收到該訊框或收到有錯的訊框（經由
    CRC-32 檢查機制），這時傳送端就會重傳此訊框，以期待再次的重傳可以成功。
    ARQ protocol 使得訊框得以在不可靠的通訊通道中提供可靠的通訊。從資訊理論的
    角度可以發現一個位元的錯誤會造成整個資料訊框的錯誤與重送。因此，如果能適
    當儲存之前發生錯誤的原始訊框資料，並比對重送但仍發生錯誤之訊框資料，有相
    當大的機會可以找出正確的原始訊框資料，也因此達到 MAC 層支援錯誤修正之能
    力。延續我們先前所研發的 CRC 網路封包錯誤更正器[1]，本論文進一步利用平行
    架構來實作 CRC 網路封包錯誤更正器以減低電路複雜度以及所花費的時間。

    Usually, data frames encapsulated in the medium access control MAC layer are
    protected by the well-known CRC-32 mechanism. The CRC-32 redundant information is
    produced by encoding the original data according to a pre-specified polynomial function.
    Upon the receiver receiving the data frame, it calculates the CRC-32 remainder of the
    received frame for determining whether the received data frame is correct or not. If the
    checking fails, the automatic repeat request (ARQ) protocol of MAC layer will be triggered to
    retransmit the erroneous data frame from transmitter to receiver. ARQ protocol is designed to
    achieve reliable transmissions over unreliable channel, and thus the packet loss probability is
    decreased. However, there is an issue that one erroneous data bit in a data frame will cause
    whole data frame to be retransmitted. This thesis proposes to properly store erroneous data
    frame(s) and combine it with the newly retransmitted frame may find out the original data
    frame. Based on our preliminary work [1], this thesis further utilizes the parallel architecture
    to construct the CRC based packet error corrector, which has the features of low circuit
    complexity and short processing time, as compared to the previously developed serial CRC
    based packet error corrector (CEC).

    CONTENTS 中文摘要 ................................................................................................................................... iv ABSTRACT ............................................................................................................................... v CONTENTS .............................................................................................................................. vi FIGURE LIST ........................................................................................................................... ix TABLE LIST ............................................................................................................................. xi 1 INTRODUCTION ................................................................................................................... 1 2 BACKGROUND ..................................................................................................................... 3 2-1 The Basic Concept of FEC ............................................................................................ 4 2-2 The Basic Concept of ARQ ........................................................................................... 5 2-3 The Basic Concept of HARQ ........................................................................................ 6 2-4 The Basic Concept of CRC Detection ........................................................................... 9 2-5 Computation of CRC ..................................................................................................... 9 2-5-1 Serial Computation of CRC ....................................................................................... 9 2-5-2 Parallel computation of CRC ................................................................................... 10 3 RELATED WORKS ............................................................................................................. 11 4 CRC BASED ERROR CORRECTOR (CEC) ...................................................................... 13 4-1 Linear Feedback Shift Register (LFSR) ...................................................................... 13 4-2 The Concept of CEC ................................................................................................... 15 4-3 The CEC Type-I Scheme ............................................................................................. 20 4-4 The CEC Type-II Scheme ........................................................................................... 21 4-5 The Analysis of Processing Delay of CEC Scheme .................................................... 25 4-5-1 Processing Delay of CEC Type-I Scheme ............................................................... 25 4-5-2 Processing Delay of CEC Type-II Scheme ............................................................. 25 5 CRC-BASED ERROR CORRECTOR USING PARALLEL ARCHITECTURE (P-CEC) 27 5-1 The P-CEC Type-I Scheme ......................................................................................... 27 5-2 The P-CEC Type-II Scheme ........................................................................................ 29 5-3 The Analysis of Processing Delay of P-CEC Scheme ................................................ 32 5-3-1 Processing Delay of P-CEC Type-I Scheme ........................................................... 32 5-3-2 Processing Delay of P-CEC Type-II Scheme .......................................................... 32 6 THE BACKGROUND OF SIMULATION .......................................................................... 33 6-1 The Flow of Digital Circuit ......................................................................................... 33 6-2 The Software of Digital Circuit-Modelsim、Quartus II ............................................. 34 6-3 Hardware Description Language-Verilog ................................................................... 34 6-4 Introduction of FPGA .................................................................................................. 35 7 SIMULATION AND VERIFICATION ................................................................................ 37 7-1 The Specification of Simulation .................................................................................. 37 7-2 The CEC Type-I Simulation and Verification ............................................................. 44 7-2-1 The CEC Type-I Simulation .................................................................................... 44 7-2-2 The CEC Type-I Verification .................................................................................. 46 7-2-3 The CEC Type-I Synthesis ...................................................................................... 47 7-3 The CEC Type-II Simulation and Verification ........................................................... 48 7-3-1 The CEC Type-II Simulation .................................................................................. 48 7-3-2 The CEC Type-II Verification ................................................................................. 49 7-3-3 The CEC Type-II Synthesis ..................................................................................... 51 7-4 The P-CEC Type-I Simulation and Verification ......................................................... 52 7-4-1 The P-CEC Type-I Simulation ................................................................................ 52 7-4-2 The P-CEC Type-I Verification .............................................................................. 53 7-4-3 The P-CEC Type-I Synthesis .................................................................................. 55 7-5 The P-CEC Type-II Simulation and Verification ........................................................ 56 7-5-1 The P-CEC Type-II Simulation ............................................................................... 56 7-5-2 The P-CEC Type-II Verification ............................................................................. 57 7-5-3 The P-CEC Type-II Synthesis ................................................................................. 59 7-6 The Comparison of CEC and P-CEC .......................................................................... 60 8 CONCLUSIONS ................................................................................................................... 61 9 REFERENCES ...................................................................................................................... 62

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