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研究生： 蔡木凱
Mu-Kai Tai
論文名稱： 改善後的階層化不完全LU法及其在二維半導體元件模擬上的應用
An Improved Levelized Incomplete LU Method and Its Application to 2D Semiconductor Device Simulation
指導教授： 蔡曜聰
Yao-Tsung Tsai
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 88
語文別： 中文
論文頁數： 49
中文關鍵詞： 階層化 、不完全LU 、混階 、模擬
外文關鍵詞： levelized, incomplete lu (ILU), mixed-level, simulation
相關次數： 點閱：15  下載：0 
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    • 在積體電路的設計和發展上，半導體的數值模擬分析扮演一個非常重要的角色。一些在實驗上或解析模型上觀察不到的元件電性，就可藉由元件的模擬來觀察。但是在半導體元件的數值模擬過程中，往往需要解非常龐大的稀疏矩陣，所以在本論文中，將就半導體元件的模擬特性來改善階層化不完全LU分解法 (Levelized Incomplete LU method)，並用來開發一個新的稀疏矩陣解法器。而在元件和半導體的混階模擬上，我們將描述載子傳輸的擴散模型藉由專業的技術加以分離，以轉換成一些等效電路元件，例如電壓控電流源、電容和電壓控制電壓源等。因此就可使用一般的電路模擬器來做混階模擬。 最後，我們將使用二極體開關電路和金氧半場效電晶體，配合新的電路模擬器進行一維和二維混階模擬，並對元件的特性進行分析和討論。在模擬過程中，我們也會比較改善後的矩陣解法和傳統解法在模擬速度上的差異。


    1. Introduction 2. Levelized Incomplete LU Method 2.1 Levelized Incomplete LU Method 2.2 Programming Techniques for Levelized Incomplete LU Method 2.2.1 Symbolic Factorization 2.2.2 Numerical Factorization 2.3 The Iteration Scheme 3. One-dimensional Semiconductor Device Simulation 3.1 1D Equivalent Circuit Model Development 3.2 Simulation of PN Diode Switching Circuit 3.3 An Improved Levelized Incomplete LU Method 4. Two-dimensional Semiconductor Device Simulation 4.1 2D Equivalent Circuit Model Development 4.2 2D Simulation of PN Diode Switching Circuit 4.3 Simulation of MOSFET Characteristics 4.3.1 Simulation of MOSFET DC i-v Characteristics 4.3.2 Simulation of MOSFET Subthreshold Current Behavior 5. Conclusion

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