在現今的系統晶片中，靜態功率消耗佔整個晶片功率消耗很大的部分。此外，靜態隨機存取式記憶體在晶片中時常超過整個晶片面積的一半以上。因此，在系統晶片中的靜態功率消耗主要會來自於靜態隨機存取式記憶體。非揮發性靜態隨機存取式記憶體在近年被提出，它能在電源關閉時保留住資料並且能在電源打開時快速的回復資料開來減少靜態隨機存取式記憶體在電源關閉時的靜態功率消耗。一個非揮發性靜態隨機存取式記憶體包含了靜態隨機存取式記憶體元件及非揮發性儲存元件。因此，測試非揮發性靜態隨機存取式記憶體會比測試靜態隨機存取式記憶體來的困難。

在這篇論文中，我們提出了應用於電阻性非揮發性靜態隨機存取式記憶體之測試及診斷技術。第一部分，我們在電阻性非揮發性靜態隨機存取式記憶體中定義了幾個憶阻器相關之錯誤。運用HSPICE來模擬及分析可能發生於電阻性非揮發性靜態隨機存取式記憶體之瑕疵。第二部分，我們針對電阻性非揮發性靜態隨機存取式記憶體之簡單靜態隨機存取式記憶體錯誤及憶阻器相關錯誤提出類行軍式測試及診斷演算法。為了要評估提出之演算法的錯誤涵蓋率，我們也實現了應用於電阻性非揮發性靜態隨機存取式記憶體之錯誤模擬器。在模擬的結果中，針對特定的錯誤所提出之測試及診斷演算法可以提供100%的錯誤涵蓋率及100%的診斷分辨率。最後，我們也實現了應用於電阻性非揮發性靜態隨機存取式記憶體之可產生類行軍式演算法的內建自我測試電路。根據模擬結果，針對一個256x8位元之非揮發性靜態隨機存取式記憶體，使用TSMC90奈米製程合成之可支援類行軍試演算法的自我測試電路約只需要642個邏輯閘。

In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Also, static random access memory (SRAM) typically occupies more than one half of the chip area. Therefore, the static power of a SOC is mainly constituted by the SRAMs. Nonvolatile SRAM has been proposed to preserve data in the power-down mode with the feature of fast power-on speed such that the static power of SRAM can be
eliminated in the power-down mode. A nonvolatile SRAM cell consists of a SRAM cell and a nonvolatile storage cell. Therefore, the testing of nonvolatile SRAM is much more difficult than that of SRAM.
In this thesis, we propose testing and diagnosis techniques for memristor-based (resistive) nonvolatile SRAMs. Firstly, several memristor-related faults of resistive nonvolatile SRAM are defined. Comprehensive defects are analyzed and simulated for the resistive nonvolatile 8-transistor SRAM using HSPICE. Secondly, we propose March-like test algorithms and diagnosis algorithms for covering simple SRAM faults and the defined memristor-related faults of resistive nonvolatile SRAMs. To evaluate the fault coverage of the proposed test algorithms, we also implement a fault simulator for nonvolatile SRAMs. Simulation and analysis results show that the proposed test and diagnosis algorithms can provide 100% fault coverage and 100% diagnostic resolutions for the targeted faults. Finally, a built-in
self-test design which can generate the March-like tests for resistive nonvolatile SRAMs is proposed. Simulation results show that only about 642 gates are needed to support March test algorithms for a 256×8-bit nonvolatile SRAM using TSMC 90nm standard cell library.

[1] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor
found,” Nature, vol. 453, no. 7191, pp. 80–83, May 2008.
[2] M.-F. Chang, C.-W. Wu, C.-C. Kuo, S.-J. Shen, K.-F. Lin, S.-M. Yang, Y.-C. King,
C.-J. Lin, and Y.-D. Chih, “A 0.5V 4Mb logic-process compatible embedded resistive
RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with
45ns random read time,” in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), 2012, pp.
434–436.
[3] P.-F. Chiu, M.-F. Chang, C.-W. Wu, C.-H. Chuang, S.-S. Sheu, Y.-S. Chen, and M.-J.
Tsai, “Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with verticalstacked
resistive memory (memristor) devices for low power mobile applications,” IEEE
Jour. of Solid-State Circuits, vol. 47, no. 6, pp. 1483–1496, June 2012.
[4] M. Durlam, P. J. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. N.
Engel, N. D. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. W. Kyler, J. J.
Ren, J. A. Molla, W. A. Feil, R. G. Williams, and S. Tehrani, “A 1-Mbit MRAM based
on 1T1MTJ bit cell integrated with copper interconnects,” IEEE Jour. of Solid-State
Circuits, vol. 38, no. 5, pp. 769–773, May 2003.
[5] Y. N. Hwang, C. Y. Um, J. H. Lee, C. G. Wei, H. R. Oh, G. T. Jeong, H. S. Jeong,
C. H. Kim, and C. H. Chung, “MLC PRAM with SLC write-speed and robust read
scheme,” in Symposium on VLSI Technology, June 2010, pp. 201–202.
[6] D. Takashima and I. Kunishima, “High-density chain ferroelectric random access memory
(chain FRAM),” IEEE Jour. of Solid-State Circuits, vol. 33, no. 5, pp. 787–792,
May 1998.
[7] H. P. McAdams, R. Acklin, T. Blake, X.-H. Du, J. Eliason, J. Fong, W. F. Kraus,
D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qiu, K. A. Remack, J. Rodriguez,
J. Roscher, A. Seshadri, and S. R. Summerfelt, “A 64-Mb embedded FRAM utilizing a
130-nm 5LM Cu/FSG logic process,” IEEE Jour. of Solid-State Circuits, vol. 39, no. 4,
pp. 667–677, Apr. 2004.
[8] H.-S. P.Wong, H.-F. Lee, S. Yu, Y.-S. Chen, Y.Wu, P.-S. Chen, B. Lee, F.-T. Chen, and
M.-J. Tsai, “Metal-oxide RRAM,” Proc. of the IEEE, vol. 100, no. 6, pp. 1951–1970,
May 2012.
[9] C. Xu, X. Dong, N. P. Jouppi, and Y. Xie, “Design implications of memristor-based
RRAM cross-point structures,” in Proc. Conf. Design, Automation, and Test in Europe
(DATE), 2011, pp. 1–6.
[10] Y.-Y. Liauw, Z. Zhang, W. Kim, A. E. Gamal, and S. S. Wong, “Nonvolatile 3D-FPGA
with monolithically stacked RRAM-based configuration memory,” in Proc. IEEE Int’l
Solid-State Cir. Conf. (ISSCC), 2012, pp. 406–408.
[11] W. Fei, H. Yu, W. Zhang, and K.-S. Yeo, “Design exploration of hybrid CMOS and
memristor circuit by new modified nodal analysis,” IEEE Trans. on VLSI Systems,
vol. 20, no. 6, pp. 1012–1025, May 2011.
[12] S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W.Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S.
Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y.Gu, S.-M. W. an F.-T. Chen,
K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, “A
4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time
and 160ns MLC-access capability,” in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC),
2011, pp. 200–202.
[13] A. Chen, M. Meneghini, D. V. Blerkom, F. Schanovsky, and T. Shaw, “Mechanisms and
performance of metal oxide resistive RAM (RRAM),” in Proc. IEEE Int’l Integrated
Reliability Workshop (IRW),, 2013, pp. 187–189.
[14] B. Mohammad, D. Homouz, and H. Elgabra, “Robust hybrid memristor-CMOS memory:
modeling and design,” IEEE Trans. on VLSI Systems, vol. 21, no. 11, pp. 2069–
2079, June 2013.
[15] M.-F. Chang, S.-S. Sheu, K.-F. Lin, C.-W. Wu, C.-C. Kuo, P.-F. Chiu, Y.-S. Yang,
Y.-S. Chen, H.-Y. Lee, C.-H. Lien, F. T. Chen, K.-L. Su, T.-K. Ku, M.-J. Kao, and
M.-J. Tsai, “A high-speed 7.2-ns read-write random access 4-Mb embedded resistive
RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes,”
IEEE Jour. of Solid-State Circuits, vol. 48, no. 3, pp. 878–891, Dec. 2012.
[16] L. O. Chua, “Memristor-the missing circuit element,” IEEE Trans. Circuit Theory,
vol. 18, no. 5, pp. 507–519, Sept. 1971.
[17] D. Biolek, Z. Biolek, and V. Biolkova, “SPICE modeling of memristive, memcapacitative
and meminductive systems,” in Prof. European Conference on Circuit Theory and
Design (ECCTD), 2009, pp. 249–252.
[18] D. Biolek, M. D. Ventra, and Y. V. Pershin, “Reliable SPICE simulations of memristors,
memcapacitors and meminductors,” Radioengineering, vol. 22, no. 4, pp. 945–968, july
2013.
[19] Y. Ho, G. M. Huang, and P. Li, “Dynamical properties and design analysis for nonvolatile
memristor memories,” in IEEE Trans. on Circuits and Systems I: Fundamental
Theory and Applications, Apr. 2011, pp. 724–736.
[20] C. E. Herdt, “Nonvolatile SRAM–the next generation,” in Nonvolatile Memory Technology
Review, 1993, pp. 28–31.
[21] A. J. V. D. Goor and S. Hamdioui, “Fault models and tests for two-port memories,” in
Proc. IEEE VLSI Test Symp. (VTS), Apr. 1998, pp. 401–410.
[22] J.-F. Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, “March-based RAM diagnosis
algorithms fo stuck-at and coupling fault,” in Proc. Int’l Test Conf. (ITC), 2001, pp.
758–767.
[23] N. Z. Haron and S. Hamdioui, “On defect-oriented testing for hybrid CMOS/memristor
memory,” in IEEE Asian Test Symp. (ATS), 2011, pp. 353–358.
[24] ——, “DfT shemes for resistive open defects in RRAMs,” in Proc. Conf. Design, Automation,
and Test in Europe (DATE), 2012, pp. 799–804.
[25] S. Hamdioui, M. Taouil, and N. Z. Haron, “Testing open defects in memristor-based
memories,” IEEE Trans. on Computers, vol. 64, no. 1, pp. 247–259, Oct. 2015.
[26] Y.-X. Chen and J.-F. Li, “Fault modeling and testing of 1T1R memristor memories,”
in Proc. IEEE VLSI Test Symp. (VTS), May 2015, pp. 1–6.
[27] S. Kannan, J. Rajendran, R. Karri, and O. Sinaoglu, “Sneak-path testing of crossbarbased
nonvolatile random access memories,” IEEE Trans. on Nanotech., vol. 12, no. 3,
pp. 413–426, May 2013.
[28] S. Kannan, R. Karri, and O. Sinaoglu, “Sneak path testing and fault modeling for
multilevel memristor-based memories,” in Proc. Int’l Conf. Comput. Des. (ICCD), 2013,
pp. 215–220.
[29] S. Kannan, N. Karimi, R. Karri, and O. Sinanoglu, “Modeling, detection, and diagnosis
of faults in multilevel memristor memories,” IEEE Trans. on Computer-Aided Design
of Integrated Circuits and Systems, vol. 34, no. 5, pp. 822–834, Jan. 2015.
[30] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable
BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, no. 1,
pp. 59–70, Jan. 1999.
[31] S. Boutobza, M. Nicolaidis, K. M. Lamara, and A. Costa, “Programmable memory
BIST,” in Proc. Int’l Test Conf. (ITC), Nov. 2005, pp. 1–10.
[32] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A builtin
self-test and self-diagnosis scheme for embedded SRAM,” in IEEE Asian Test Symp.
(ATS), Dec. 2000, pp. 45–50.
[33] P.-C. Tsai, S.-J. Wang, and F.-M. Chang, “FSM-based programmable memory BIST
with macro command,” in Proc. IEEE Int’l Workshop on Memory Technology, Design
and Testing (MTDT), Aug. 2005, pp. 72–77.
[34] K. Zarrineh and S. J. Upadhyaya, “On programmable memory built-in self test architectures,”
in Proc. Conf. Design, Automation, and Test in Europe (DATE), Mar. 1999,
pp. 708–713.
[35] ——, “On programmable memory built-in self test architectures,” in Fault-Tolerant
Computing, June 1999, pp. 352–355.
[36] B.-C. Bai, K.-L. Luo, C.-A. Chen, Y.-W. Chen, H. W. M, C.-L. Hsu, L.-C. Cheng, and
J. C.-M. Li, “Back-end-of-line-defect analysis for Rnv8T nonvolatile SRAM,” in IEEE
Asian Test Symp. (ATS), 2013, pp. 123–127.
[37] P.-F. Chiu, M.-F. Chang, S.-S. Sheu, K.-F. Lin, P.-C. Chiang, C.-W. Wu, W.-P. Lin,
C.-H. Lin, C.-C. Hsu, F.-T. Chen, K.-L. Su, M.-J. Kao, and M.-J. Tsai, “A low store
energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low
power mobile applications,” in Proc. IEEE Symp. VLSI Circuits (VLSIC), 2010, pp.
229–230.
[38] W. Wei, K. Namba, J. Han, and F. Lombardi, “Design of a nonvolatile 7T1R SRAM
cell for instant-on operation,” IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp.
905–916, Sept. 2014.
[39] S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile SRAM (NV-SRAM) using functional
MOSFET merged with resistive switching devices,” in Proc. IEEE Custom Integrated
Circuits Conference (CICC), 2009, pp. 531–534.
[40] S.-S. Sheu, C.-C. Kuo, M.-F. Chang, P.-L. Tseng, C.-S. Lin, M.-C. Wang, C.-H. Lin,
W.-P. Lin, T.-K. Chien, S.-H. Lee, S.-C. Liu, H.-Y. Lee, P.-S. Chen, Y.-S. Chen, C.-C.
Hsu, F.-T. Chen, K.-L. Su, T.-K. Ku, M.-J. Tsai, and M.-J. Kao, “A ReRAM integrated
7T2R non-volatile SRAM for normally-off computing application,” in Proc. IEEE Asian
Solid-State Circuits Conference (A-SSCC), 2013, pp. 245–248.
[41] S. Hamdioui and A. J. V. D. Goor, “An experimental analysis of spot defects in SRAMs:
realistic fault models and tests,” in IEEE Asian Test Symp. (ATS), 2000, pp. 131–138.
[42] H.-C. Shih, C.-Y. Chen, C.-W. Wu, C.-H. Lin, and S.-S. Sheu, “Training-based forming
process for RRAM yield improvement,” in Proc. IEEE VLSI Test Symp. (VTS), May
2011, pp. 146–151.
[43] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in
Defect and Fault Tolerance in VLSI Systems, Nov. 1999, pp. 165–173.
[44] C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Fault simulation and test algorithm
generation for random access memories,” IEEE Trans. on Computer-Aided Design
of Integrated Circuits and Systems, vol. 21, no. 4, pp. 480–490, Apr. 2002.
[45] K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, “RAMSES-FT: a
fault simulator for flash memory testing and diagnostics,” in Proc. IEEE VLSI Test
Symp. (VTS), Apr. 2002, pp. 281–286.