單電子電晶體發展至今，各個研究團隊利用半導體材料製作量子點，雖然目前已經有許多製作量子點的技術陸續被研發出來，但大多都面臨了再現性低與量子點大小位置無法掌控的問題。本論文研究討論利用選擇性氧化複晶矽鍺以形成鍺量子點的技術，除了可利用鍺材料的電子費米波長較矽材料的費米波長大，來克服矽量子點微縮的問題；也可利用矽鍺合金的選擇性氧化克服了量子點需要精準的微影蝕刻技術，且也不需要在高成本的絕緣層上覆矽基板製作等的問題。而本論文實驗調變各種多邊形圖案之孔洞大小，精確地控制鍺量子點之數量與位置。利用多邊形側壁為二氧化矽的條件，且各圖案的內心圓半徑等於或小於15 nm時，可觀察到單一顆的鍺量子點分佈在多邊形圖案中間。而多邊形側壁為氮化矽的條件時，當各圖案的內心圓半徑等於或小於15 nm，也會觀察到單一顆的鍺量子點分佈在多邊形圖案的中間；但當內心圓半徑介於30 nm與70 nm之範圍內，鍺量子點會分佈在多邊形圖案的邊緣甚至是角落。於是我們可利用此方法，對鍺量子點定位與定量。單一顆鍺量子點可供單電子電晶體應用；而兩顆、三顆等等的量子點做為偶合量子點之用。

　Recently semiconductor quantum dots have been extensively researched, but the most of the forming quantum dots techniques face the problems of low reproducibility and poor controllability on the position and the number of quantum dots.
　This thesis demonstrates the feasibility of positioning and numbering Ge quantum dots by means of oxidizing SiGe polygonal cavities with SiO2 and Si3N4 spacers. For polygons with SiO2 spacers have an inner circle radius less than 15 nm, one Ge quantum dot is formed in the center of cavity with a dot size of 10.4 nm. In contrast, polygons with Si3N4 spacers have the same inner circle radius, one Ge quantum dot formed in the center of triangle, square, and pentagonal cavities, with a dot size of 10.4 nm, 12.6 nm, and 10.9 nm. For a triangle with Si3N4 spacers have the inner circle radius between 35 and 40 nm, Ge quantum dots exist only at the corners of triangle, with an average dot size between 9.8 ± 0.7 nm and 10.2 ± 0.6 nm.
　Using this method, it is reasonable to expect that effective single-electron transistors and coupled quantum dots devices could be realized.

[1]　陳啟東, “單電子電晶體簡介,” 物理雙月刊, 第二十六卷, 第三期, 483頁, 2004年.
[2]　T. Hiramoto et al., “Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors,” Appl. Phys. Lett., vol. 85, p. 6233, 2004.
[3]　S. Lee et al., “Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor,” Appl. Phys. Lett., vol. 92, p. 073502, 1998.
[4]　T. Hiramoto et al., “Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic series resistance,” J. Appl. Phys., vol. 91, p. 6725, 2002.
[5]　T. Hiramoto et al., “Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor field-effect transistors and single-electron transistors,” J. Appl. Phys., vol. 103, p. 053709, 2008.
[6]　S. Y. Chou et al., “Single hole quantum dot transistors in silicon,” Appl. Phys. Lett., vol. 67, p. 2338, 1995.
[7]　S. Y. Chou et al., “Observation of quantum effects and Coulomb blockade in silicon quantum-dot transistors at temperatures over 100 K,” Appl. Phys. Lett., vol. 67, p. 938, 1995.
[8]　L. Zhuang et al., “Silicon single-electron quantum-dot transistor switch operating at room temperature,” Appl. Phys. Lett., vol. 72, p. 1025, 1998.
[9]　L. C. Ma et al., “Electrostatic funneling for precise nanoparticle placement: a route to wafer-scale integration,” Nano Letters, vol. 7, p. 439, 2007.
[10]　S. Onclin et al., “Engineering the silicon oxide surface using self-assembled monolayers,” Angew. Chem. Int. Ed., vol. 44, p. 6282, 2005.
[11]　R. K. Smith et al., “Patterning self-assembled monolayers,” Prog. Surf. Sci., vol. 75, p. 1, 2004.
[12]　Y. Nakamura et al., “Al/Al2O3/Al single electron transistorsoperable up to 30 K utilizing anodization controlled miniaturization enhancement,” Appl. Phys. Lett., vol. 68, p. 275, 1996.
[13]　W. Chen et al., “Coulomb blockade at 77 K in nanoscale metallic islands in a lateral nanostructure,” Appl. Phys. Lett., vol. 66, p. 3383, 1995.
[14]　D. L. Klein et al., “Anapproach to electrical studies of single nanocrystals,” Appl. Phys. Lett., vol. 68, p. 2574, 1996.
[15]　K. Matsumoto, “STM/AFM nano-oxidation process to room-temperature-operated single-electron transistor and other devices,” Proceedings of the IEEE, vol. 14, p. 612, 1997.
[16]　M. E. Rubin et al., “Imaging and spectroscopy of single InAs self-assembled quantum dots using ballistic electron emission microscopy,” Phys. Rev. Lett., vol. 77, p. 5268, 1996.
[17]　Y. Takahashi et al., “Size dependence of the characteristics of Si single electron transistors on SIMOX substrates,” Electron Devices IEEE Trans., vol. 43, p. 1213, 1996.
[18]　M. Saitoh et al., “Room-temperature demonstration of integrated silicon single-electron transistor circuit for current switching and analog pattern matching,” IEDM Tech. Dig., p. 187, 2004.
[19]　T. Hiramoto et al., “Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor field-effect transistors and single-electron transistors,” J. Appl. Phys., vol. 103, p. 053709, 2008.
[20]　P. W. Li et al., “Growth kinetics and related physical/electrical propertiesof Ge quantum dot formed by thermal oxidation of Si1-xGex-on-insulator,” Nanotechnol., vol. 18, p. 145402, 2007.
[21]　陳冠宏, “應用於高效率單電子元件鍺量子點之研製：鍺量子點定位與定量之探討,” 國立中央大學, 碩士論文, 2009年.
[22]　黃郁婷, “垂直式單電子/電洞電晶體之研製,” 國立中央大學, 碩士論文, 2009年.