隨著半導體製程技術不斷的進步，積體電路單晶片化的系統已成趨勢，當系統整合時，電路上同步時脈訊號的重要性便日益彰顯，若時脈的抖動量過大或具相位偏移時，會造成系統在操作上錯誤。有鑑於此，此系統上便選擇鎖相迴路(Phase-Locked Loop ,PLL)或延遲鎖定迴路(Delay-Locked Loop , DLL)來當作參考時脈來源，但就目前單晶片化的趨勢與操作頻率不斷的提升，要直接針對鎖相迴路或延遲鎖定迴路的輸出時脈信號抖動量進行量測已變成相當困難，此外利用外部儀器量測不僅需花費高額的成本，再加上外部儀器在進行量測時會引入雜訊，影響其結果，基於上述原由，內建自我測試電路便因此產生。
本論文提出的「應用於6 GHz時脈產生器之高解析度抖動量測電路」以提高量測解析度、降低製程變異影響為設計準則，本論文採用自我取樣的方式搭配具多相位取樣電路的作法改善傳統抖動量測電路需額外信號作為參考信號源。此外為了能夠量測到時脈信號微小抖動量，在電路中加上時間放大電路(Time Amplifier Circuit)以提高量測的精準度。
本次抖動量測電路是利用TSMC 90 nm 1P9M製程來設計，完成應用6 GHz時脈產生器之高解析度抖動量測電路，解析度可逹到1 ps左右。

As the improvement of semiconductor technology, VLSI circuit has developed in a system on chip (SoC). If the clock jitter is excessive or phase deviation, the mistakes of system operation will be enerated. In view of this problem, clock synchronization circuits such as PLLs and DLLs will be used the clock source. But on a tendency toward SoC system and high operating speed, it is difficult to measure the output clock jitter of the PLL circuit directly. In addition, using external measuring equipments not only need to take the high cost of equipment and noise caused by the test results also affected. For these reasons, the built-in self-test circuitry for clock jitter measurement can be produced.
This thesis on-chip high resolution jitter measurement circuit with self-calibration technique for 6 GHz clock generator is proposed to improve the measurement resolution. It can reduce process variation effect. The conventional jitter measurement circuits need an additional signal as the reference source. In this thesis, the use of self-refereed method with multi-phase sampler can eliminate the problems of the reference source. It also reduces the circuit mismatch. In addition, in order to measure the tiny clock jitter in high-speed serial link, the proposed circuit uses the time amplifier circuit to increase the high accuracy. However, process variation will also influence the measure results. Therefore, the first auto-calibration and second calibration circuits are used to compensate the process variation.
This jitter measurement circuit is designed in TSMC90nm 1P9M process. It can measure the 6GHz clock jitter. The resolution of the overall circuit is 1ps .

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