隨著CMOS製程技術進入奈米時代，元件尺寸不可能再毫無限制的縮減，而且許多在過去大尺寸元件不曾出現的問題，也隨著尺寸的縮減逐步浮上檯面，例如短通道效應(short channel effect)所造成的高電場及薄氧化層所造成的漏電流等非理想效應，因此單電子元件已開始倍受矚目。而在單電子元件中，最重要的核心技術在於量子點的製作。為了要與現今CMOS製程技術相容，利用矽材料開發單電子電晶體最為廣泛，一般製作矽基材量子點與單電子電晶體之方式，需要利用超高解析度之電子束微影技術(E-beam lithography)、複雜的蝕刻等製程來縮小量子點的尺寸，但通常伴隨著高成本、製程掌控不易及再現性低等缺點。而本實驗室已成功開發出利用〝矽鍺選擇性氧化法〞形成奈米級的鍺量子點，這是一種簡單且與CMOS製程相容的方法。
本論文之研究重點，利用〝矽鍺選擇性氧化法〞製作鍺量子點共振穿隧二極體。在室溫下，經由光的激發可觀察到明顯的共振震盪、負微分電導現象，並且在實驗上，對通過鍺量子點之暫態電流作研究，在不同的偏壓下，觀察到類似鋸齒狀的電流行為，以及類似正弦波電流行為。並提出相對應的模型解釋所觀察到的實驗現象，此模型是建立在單電子穿隧過量子點和缺陷(trap)彼此間相互影響的觀念上。

As CMOS technology toward to Nano-generation, the reduction of device dimension doesn’t shrink unlimitedly. And many problems would appear as shrinking device dimension which never appear in large dimension devices. For example, short channel effect would induce high electric field and thin gate oxide thickness would induce leakage. So that single-electron device has attracted a lot of attention. The key point of single-electron device is the formation of quantum dots. In order to be compatible with CMOS technology, using Si-based material is the extensive method to develop single-electron device. In general, the methods of developing Si quantum dots and single electron device are using ultra-high resolution of E-beam lithography and complex etching process. But they have high cost, not easy to control and reproduction questions. We have developed “the selectivity oxidation of SiGe ” successively to form Ge quantum dots. It is a simple and CMOS compatible method.
The focal point of this thesis is using “the selectivity oxidation of SiGe ” method to fabricate Ge-QD RTD. We have experimentally studied the time-averaged and transient current of a Ge-QD RTD. The tunneling current not only displays additional peaks but also exhibits enhanced PVCR with NDC under photoexcitation. A model based on the interplay of a trap and single-electron tunneling through a small QD is proposed to explain the observed features of transient current characteristics.

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