現今新興的超低功率消耗的應用，越來越受到大家的關注與重視。為了達到超低功率消耗的需求，以延長產品使用時間，次臨界區(Sub-threshold)電路設計提供了一種解決方法，藉由操作在極低電壓 (Vdd<Vth)的方式，可以降低動態功率消耗及漏電流消耗。然而，當電路操作在次臨界區，其電路的特性及設計方式，將完全不同於一般的設計，極需研發新的EDA輔助軟體。本論文提出一套自動化設計次臨界區類比電路的EDA輔助軟體，可以解決不同操作區間及雜訊干擾問題，並使用線性規劃(linear programming)來找尋最佳解，降低類比工程師手動調整電路設計的時間，加快設計時程。由模擬結果的數據觀察可知，本自動化工具產生的放大器電路，確實能根據不同需求找到不同的最佳電晶體尺寸，得到考量放大率、面積、雜訊的最佳解。

Power has become the primary design constraint for chip designers today. To reduce power and increase service time, low-voltage low-power design becomes more and more important. One of the possible ways to achieve this goal is sub-threshold circuit design. By operating transistors at the region that Vdd is less than the transistor threshold voltage (Vdd<Vth), such kind of sub-threshold designs have low dynamic power dissipation and low leakage current. However, the circuit characteristics and design method in sub-threshold region are different to typical design style. There is an urgent need for new analog EDA tools. In this thesis, an automatic sub-threshold analog EDA tool is presented to generate the required circuits with noise consideration. In this tool, linear programming is adapted to find the optimal solution. It can reduce the manual design time and improve the productivity. According to the simulation results, the automatically generated OPA can meet the requirements of different users and reach the optimal solution with gain, area, and noise consideration.

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