DVB-T2(second generation digital terrestrial television broadcasting system)是歐規數位電視廣播(DVB)指導委員會於2009年制定出來的第二代數位電視地面廣播標準。相較於原先DVB-T規格，新一代的DVB-T2有較佳的錯誤更正力，進而提升了系統的通道容量，適合高畫質電視的使用。
其中，DVB-T2規格中使用Low Density Parity Check (LDPC) 碼作為內編碼，提供了很好的錯誤更正能力。然而，LDPC碼的解碼演算法Sum-Product Algorithm，需要相當複雜的運算不利硬體實現，因此選用效能相當接近，經過修改的Min-Sum Algorithm來實現我們的LDPC解碼器。
我們將DVB-T2規格中提供的校驗矩陣(Parity-Check Matrix)轉化為QC-LDPC的排列，這有利於我們使用其中單位矩陣的旋轉量，簡單的表達出校驗矩陣的特性，這讓解碼器在不同的碼率時，只需得到校驗矩陣的旋轉量後，即能開始運作。而在硬體實現的層面上，平行處理的數量同時代表的是解碼器的速度以及複雜度，考量系統輸出率(Throughput Rate)與硬體實現複雜度間的平衡，在不影響DVB-T2整體系統的前提下，文中設計將呈現QC form的校驗矩陣區塊，以兩種方式(Partial Parallel & Bit-Slice)分為更小的子區塊分次進行處理，讓解碼器的速度與複雜度同時下降。

DVB-T2, which is an abbreviation for Digital Video Broadcasting – Second Generation Terrestrial, is a draft standard ratified by the DVB Steering Board on June 26, 2008. Compared to the original DVB-T specification, the new standard increases the channel capacity to fulfill the need for High Definition TV transmission with satisfactory error performance.
The DVB-T2 system uses multi-rate Low Density Parity Check (LDPC) codes, which are characterized by multiple parity-check matrices, as the inner encoding to provide satisfactory error performance. The optimal decoding algorithm for LDPC code, Sum-Product Algorithm, requires very complex calculation and is not favorable for hardware implementation. Therefore, we use the Modified Min-Sum Algorithm, which provide a error performance not far from the Sum-Product Algorithm, as the decoding algorithm for hardware implementation. Although the Parity-Check matrices of the multi-rate LDPC codes specified in the DVB-T2 standard do not show any Quasi-Cyclic (QC) form, they can be transformed to a QC form through specific column/row-wise cyclic permutations. In this thesis, we modify a reconfigurable hardware decoder architecture, which suitable for general QC-LDPC codes, for implementation of such multi-rate DVB-T2 LDPC decoders. The reconfiguration is simply achieved through a lookup table load with corresponding parameters. Moreover, to lower the hardware implementation complexity, we propose a bit-slice architecture with a trade off in the system throughput rate.

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