本論文主要提出微波及毫米波訊號源關鍵電路，內容包含二個K頻段的頻率倍頻器、一個X頻段的四相位壓控振盪器及一個X頻段的鎖相迴路。
第二章使用穩懋0.15 μm砷化鎵之增強式應變式異質接面高遷移率電晶體製程及轉導增強式(Gm-boosted)技術在K頻段倍頻器(K-band frequency doubler)之研製。電路架構分成差動輸入(differential input)及單端輸入(single-end input)兩部分介紹，轉導增強式技術是利用增強輸入端的電壓擺幅，以減少輸入端的驅動功率，提昇整體轉換增益。第一部分介紹單端輸入共源級轉導增強式倍頻器，在量測輸入0 dBm時，可達到0.9 dB的轉換增益，3 dB輸出頻寬範圍為37到43 GHz，3 dB頻寬比為15%。在38 GHz輸出頻率時，量測輸出飽和功率等於0 dBm，晶片面積為0.9×0.8 mm2。第二部分介紹差動輸入共閘級轉導增強式倍頻器，同時使用被動式電容交叉耦合技術，主動式共閘級轉導增強式為增益提昇的主要來源 ，而被動式電容交叉耦合在不額外增加直流功耗下，額外提昇本身轉導級的增益，詳細的設計流程在此呈現，包含比較共源級及共閘級轉導提昇的頻寬及設計考量。在量測差動輸入7 dBm達到3.3 dB的轉換增益及27.8%的3 dB頻寬比(3 dB頻寬範圍為31到41 GHz)，在38 GHz輸出頻率時，量測輸出飽和功率等於7 dBm，晶片面積為1.2×0.8 mm2。
第三章提出應用在X頻段的低相位雜訊高功率高效率四相位疊接迴路型壓控振盪器，使用台積電0.18 μm互補式金屬氧化物半導體製程設計實現。電路利用交叉耦合(cross-coupled)將兩個共源共閘(cascode)疊接迴路型振盪器接成差動壓控振盪器，並利用背閘極將兩個差動壓控振盪器進行四相位耦合。其中，背閘極耦合技術減少額外的直流消耗及降低相位雜訊，詳細的設計流程、四相位分析和相位雜訊計算也在此呈現。量測輸出功率和直流轉換效率分別為10 dBm和11.2%，振盪頻率為9.3到9.5GHz，相位誤差和振幅誤差為0.26˚及0.2 dB，因為使用具有高品質因子(quality factor)的T型阻抗匹配網路，所以大幅降低振盪器的相位雜訊，量測相位雜訊在1 MHz頻率偏移時可優於-125 dBc/Hz，晶片面積為1.3×1.28 mm2。
第四章將論文所提出X頻段四相位壓控振盪器整合至鎖相迴路(PLL)系統中， 鎖相迴路包含四相位壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器、兩級電流模式除頻器及四級單相位時序除頻器。電路是使用台積電0.18 μm互補式金屬氧化物半導體製程設計並實現，總除數為64，頻率範圍為9.28至9.32 GHz。 藉由低抖動(jitter)的參考頻率及低雜訊的四相位壓控振盪器結合至鎖相迴路中，使鎖相迴路具有穩定及低相位雜訊的特性。量測相位雜訊在1 MHz頻率偏移時為-108.7 dBc/Hz，量測方均根值(rms)抖動(jitter)為466 fs，量測雜訊抑制(spur suppression)小於-80 dBc，此電路晶片面積為1.5×1.6 mm2。最後，在第五章總結此研究成果。

In this thesis, several key components of microwave and millimeter-wave signal sources are presented, including two K-band frequency doublers, an X-band quadrature voltage-controlled oscillator and an X-band phase locked-loop (PLL).
In Chapter 2, the two K-band frequency doublers using Gm-boosted technique in WIN 0.15-μm GaAs E-mode pHEMT are introduced. The circuit design consists of a differential input frequency doubler and a single-end input frequency doubler. When the Gm-boosted technique is employed in the frequency doubler designs, the input driving power decreases and the conversion gain enhances because of the boosted input voltage swing. The proposed single-end input frequency doubler exhibits a conversion gain of 0.9 dB when input power is 0 dBm, a fractional bandwidth of 15% and a fractional bandwidth range from 37 to 43 GHz. The maximum saturated output power (Psat) is 0 dBm at 38-GHz output frequency. Meanwhile, the capacitive cross-coupling technique is also adapted for the differential input frequency doubler. The common-gate (CG) Gm-boosted stage provides gain dominantly and the cross-coupling capacitor further boosts the gain of the doubly Gm-boosted stage without adding additional dc power consumption. The detail design procedure is also presented. The comparisons of the bandwidth using Gm-boosted technique between a common-source (CS) Gm-boosted stage and a CG Gm-boosted stage are addressed. The proposed differential input Gm-boosted stage frequency doubler exhibits a conversion gain of 3.3 dB when input power is 7 dBm, a fractional bandwidth of 27.8% and the fractional bandwidth range from 31 to 41 GHz. The maximum output Psat is 7 dBm at 38-GHz output frequency.
In Chapter 3, the X-band low phase noise high power high efficiency quadrature voltage-controlled oscillator (QVCO) using TSMC 0.18-μm CMOS is proposed. Two cascade oscillators are combined using cross-coupled technique. Meanwhile, the coupling between the two differential VCOs is designed using a back-gate coupling topology for the QVCO. DC power and phase noise can be reduced due to the back-gate coupling topology. The detail design procedure, quadrature analysis and phase noise calculation are addressed. The proposed high power high efficiency QVCO exhibits an output power of 10 dBm and a dc-to-RF conversion efficiency of 11.2%. The measured tuning range is 200 MHz (from 9.3 GHz to 9.5 GHz). The measured phase error is 0.26˚ and amplitude error is 0.2 dB. The phase noise is reduced due to using TEE matching network experiencing high quality factor. The measured phase noise is -125 dBc/Hz at 1-MHz offset. The chip size is 1.3×1.28 mm2.
In Chaptor 4, the proposed QVCO merged with PLL is presented. The building blocks of the PLL include a QVCO, a phase-frequency detector, a charge pump, a loop filter and two-stage common-mode logic dividers and four-stage true single phase clocking dividers. The PLL is implemented using TSMC 0.18-μm CMOS process. The measured frequnecy is from 9.28 GHz to 9.32 GHz. The measured phase noise is -108.7 dBc/Hz at 1-MHz offset with an rms jitter of 466 fs. The measured spur suppression is lower than -80 dB. The chip size is 1.3×1.28 mm2.
Finally, the conclusion is given in Chaptor 5.

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