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研究生： 林志雄
Chi-Shiung Lin
論文名稱： 兆元位元率之平行化可適性決策回饋等化器設計與實作
Design and Implementation of Multi-Giga Bit Parallel Adaptive Decision Feedback Equalizer
指導教授： 周世傑
Shyh-Jye Jou
薛木添
Muh-Tian Shieu
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 94
語文別： 英文
論文頁數： 68
中文關鍵詞： 高速等化器
外文關鍵詞： equalizer
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    • 高速網際網路與傳輸技術在近年來蓬勃的發展，使得目前通訊系統已經達到相當快的傳輸速率，根據近年來所訂定的通訊系統標準，系統的符碼速率(Data rate)已達到每秒數億符碼(Gbps)，甚至每秒千億符碼的數量級。
    隨著符碼速率的大量增加，交互符碼干擾(Inter-symbol interference, ISI)是經常存在，且對傳輸訊號有著嚴重的干擾，可適性決策回饋等化器(Adaptive decision feedback equalizer, ADFE)在目前的通訊系統中佔了相當重要的角色，因為一個好的等化器決定了整個系統的傳輸速率和符碼錯誤率(Bit error rate, BER)，且佔了相當多的運算量。
    然而，可適性決策回饋等化器及最小均方演算法(LMS algorithm)的回授架構限制了等化器的速度，要達到如此的高的符碼速率是相當困難的。本論文依據IEEE 802.3ae工作小組所訂定的百億位元乙太網路系統(10-Gigabit Ethernet System)規格，提出了一個高速等化器設計，並且可以適用於10GBase-LX4光纖通訊系統。我們以台積電0.13μm CMOS 製程完成了3.5Gbps全數位可適性決策回饋等化器之晶片設計，此晶片面積為1.55 × 1.55 mm2，消耗功率在3.5Gbps的取樣速率下則為110 mW。

    Internet and data transmission technique are going to grow fast, the trend of recent Ethernet system will make a high effort to provide high data rate services. According to the related standard about high speed wire-lined communication system, the data rate is more than gigabits per second, even several gigabits per second.
    Hence, for the high transmitted data rate, the Inter-Symbol Interference (ISI) effect always exists, and it is serious and dominant for the signal distortion. The design of Adaptive Decision Feedback Equalizer (ADFE) is very important because it determines the system performance, such as Bit Error Rate (BER) and data rate. The computation cost of ADFE is also large for hardware implementation.
    The conventional ADFE and the Least-Mean-Square (LMS) algorithm inherently have feedback inside the data flow and the operating frequency is limited by the feedback structures. The internal feedback or recursive in the architecture algorithms makes it difficult to implement systems concurrency in the form of either pipelined or paralleled processing. This thesis provides a high speed equalizer design, and it is suitable for the 10GBase-LX4 Ethernet system in IEEE 802.3ae standard (IEEE 802.3ae Ad-hoc database). We design and implement an all digital 3.5Gbps blind ADFE based on the TSMC 0.13 μm CMOS technology. The implementation shows that the chip area is 1.55 × 1.55 mm2 with operation up to 3.5 Gbps using 1.2-V supply and dissipates 110 mW.

    Abstract i Contents iii List of Figures v List of Tables viii Chapter 1 Introduction 1 1.1 Motivation 1 1.1.1 Design Challenge for High Speed Equalizer -- Loop Bound Limitation 6 1.1.2 Design Challenge for High Speed Equalizer -- Large Overhead of Hardware Complexity 7 1.2 Thesis Organization 8 Chapter 2 Overview of 10-Gigabit Ethernet System (10GBase-LX4) 9 2.1 Channel Models 9 2.2 10GBase-LX4 Ethernet System 11 2.3 Summary of Simulation Environment 13 2.4 Review of Equalizer Designs 13 2.4.1 Linear Equalizer 14 2.4.2 Non-Linear Equalizer 16 2.5 Introduction of Adaptive Algorithm 18 2.5.1 LMS Algorithm for Adaptive Decision Feedback Equalizer 18 2.5.2 Conventional Adaptive Decision Feedback Equalizer Architecture 21 Chapter 3 System Simulation Results 23 3.1 BER versus ADC Bit Number 24 3.2 BER versus SNR 27 3.3 Coefficient Values 28 3.4 The LMS Algorithm with Delayed Coefficient Adaptation 31 3.5 Symbol Diagrams 33 Chapter 4 VLSI Architecture Design of a High-Speed Adaptive Decision Feedback Equalizer 34 4.1 Feed-Forward Equalizer Design for High-Speed Applications 35 4.2 Feed-Backward Equalizer Design for High-Speed Applications 38 4.2.1 Conventional DFE 38 4.2.2 Reformulated Coefficient-Select (RCS) DFE 39 4.2.3 Stage-by-Stage Adder Tree 40 4.2.4 Retiming Form 42 4.2.5 Stage-by-Stage Carry Save Adder Tree with FFE 42 4.3 The LMS Algorithm with Delayed Coefficient Adaptation 43 4.4 New Types for Reformulated DFE 45 4.4.1 Reformulated Look-Ahead (RLA) DFE 45 4.4.2 New RCS DFE 48 4.4.3 Comparisons 49 Chapter 5 Chip Implementation 53 5.1 Design Flow 53 5.2 Chip Implementation 55 5.2.1 Design Flow for Place and Route 55 5.2.2 Pad and Measurement Considerations 58 5.2.3 Chip Summary 61 Chapter 6 Conclusions 65 Reference 67

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