當超大型積體電路設計演進到奈米時代，功率完整性問題變成限制電路效能的最主要原因之ㄧ。電源線上的電壓降以及同步切換雜訊是兩個影響功率完整性的常見問題。因為這兩種雜訊都跟電源上的電流大小以及變化程度有極大的關係，因此，必須要有準確的電流源波形才能準確的分析電壓源雜訊。
在傳統的設計流程中，電壓源上的電流波形必須依靠電晶體層級之電路模擬才能獲得準確的估測，因此必須在電路設計流程的後期才能進行電源完整性的驗證。對大電路而言，想要模擬整個電路需要龐大的計算時間以及資源，這種模擬的方式就顯得不太實際。如果在這個階段發現了電源完整性的問題，設計者通常也只能加寬電源線或是增加降耦合電容來改善電壓降的現象。然而，若是在設計流程的初期就可以大略估計電壓源上的電流波形，就能使用更多有效率的方法來消除功率雜訊的影響，例如重新合成或是電源閘控技術
在現今的設計流程之中，使得電流波形無法在設計初期估計出來的原因主要有兩個。第一個原因是在設計初期缺乏跟功率源有關的資訊。在暫存器資料轉移層級之中，所有節點的電壓均被視為邏輯值1和0，設計者僅考慮電路功能的正確性而忽略了電壓降效應。在邏輯閘層級，雖然有更多相關的設計資訊，例如電壓值以及每個邏輯閘的功率消耗。然而，由於缺少電壓源上的電流大小及其變化率，這些資訊仍然不足以用來分析電壓降的大小。
第二個原因是缺少電壓源雜訊對電路行為的影響。在現今的電壓降分析之中，電源網路常被用簡化成簡單的電阻電感電容網路，而切換電流被簡化為簡單的電流源。這些電流源是在理想的電流網路中被模擬出來的。然而，有受到電壓源雜訊影響的電流波形跟理想電流網路中量測到的電流會有些許不同。因此，若是使用理想的電流波形來估計電壓降的大小，通常會有一定的誤差。
本篇論文提出了一系列可在設計初期估計電壓降分析之電流波形估計方法。對於邏輯閘層級的電路，本論文提出了僅需要標準元件庫資料的分析式電流模型[33] [34]，也提出了修正標準元件庫資料的方法來考量電源雜訊的影響[35] [36]，以提供更準確的估測結果。對暫存器資料轉移層級的設計，本論文提出了改良式的區塊層級電流模型來提供必要的電流資訊[37] [38]。對於電源雜訊的影響，也提出了修正轉移函數的方式來修正電流波形[38]。如果能將這些估測技術整合進入現今的設計流程之中，設計者便可在設計層級盡量避免電壓降的問題。使得電路設計更加迅速與正確。

As VLSI technology advances into the nanometer era, the power integrity problem is becoming one of the most critical issues that limit design performance. IR-drop and simultaneous switching noise (SSN) are two major power supply noises (PSNs) causing power integrity problems. Because these two noises are highly dependent on the magnitude and slope of supply currents, accurate supply current waveforms are required for precise analysis.
Traditionally, accurate supply current waveforms can only be obtained using the transistor-level circuit simulation. Therefore, in the present design flow, a power integrity check is performed mostly in late design stages. This approach may be impractical for large designs because simulating the entire design at the transistor level requires great computational resources. If a power integrity problem is identified, designers often increase the width of the supply lines or add decoupling capacitors to reduce the IR-drops. However, if the supply current waveforms can be obtained in early design stages, more efficient IR-drop reduction technologies can be used to reduce the power supply noise, such as re-synthesis and power-gating.
In the present design flow, supply current waveforms are not easily obtained in early design stages because of two major reasons. The first reason is the lack of supply voltage information at the front-end design level. All internal voltages are viewed as logic-1 and logic-0 at the RT (Register Transfer)-level. Designers only consider the functional correctness of designs and ignore the IR-drop effects. At the gate level, more information is available, such as the supply voltage and the average power of each standard gate. However, this power information is inadequate in estimating IR-drops because it cannot provide the slope and maximum amplitude of the supply current for IR-drop analysis.
The second reason is the lack of dynamic changes on the power information under different supply noises. In the conventional IR-drop analysis, power girds are modeled as an RLC network, and the switching currents are modeled as simple current sources. These current sources are obtained by simulating switching circuits with ideal supply voltages. However, the supply current waveforms with the supply noises are different, compared to ideal ones. Extra errors may occur if the ideal current waveform is used to estimate the situations under supply noises.
This dissertation proposes several front-end supply current waveform modeling techniques to support the IR-drop at early design stages analysis. For gate-level designs, an analytical current model is proposed [33] [34], which uses standard library information to estimate supply current waveforms. The library adjustment method under supply noises is also proposed [35] [36] for more accurate estimation of real supply noises. For functional-level analysis, an improved macro-level current model is proposed [37] [38] to provide the essential current information. The waveform transformation method also proposed to modify the generated current waveforms to reflect the supply noise effects [38]. If these techniques are integrated in the present design flow, power integrity checks can be performed at early design stages to prevent IR-drop issues.

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