乙太網路通訊協定為視訊串流應用最被廣泛使用的標準，傳統使用通用型微
處理器以嵌入式軟體實現視訊串流的網路服務，需要耗費非常大量運算成本、功
耗及系統資源，往往造成系統效能的瓶頸。
本研究在 FPGA 平台上設計並實現了一個全硬體化的高速嵌入式視訊串流
系統。此一系統包含兩大模組：gigabit UDP/IP 卸載引擎，以及影像擷取及視訊
串流格式化模組。UDP/IP 卸載引擎又切割成傳輸層控制器、網路層控制器和連
結層控制器等子模組，同時我們設計一個上層的管線化控制器以整合這些高速的
硬體模組。影像擷取及視訊串流格式化模組則由CMOS 攝影機取像控制器和隨
後的格式化產生器及最後的定位封裝產生器所構成。
結果顯示，我們的硬體化UDP/IP 卸載引擎使用的硬體資源極為精簡，電路
面積不到3K 邏輯單元(Logic Element, LE)，記憶體需求為87 Kbit，此一結果將
十分利於未來超低成本ASIC 晶片的量產。此外，我們在125MHz 系統時脈的
FPGA 平台即可達到gigabit 等級的網路資料流處理，解決了傳統使用微處理器的
效能瓶頸。

The most widely used standards for delivering streaming video web services are based on ethernet protocol combined with a traditional general-purpose microprocessor with embedded software. The performance bottleneck of this architecture is that it requires a large amount of computing power, system resources, and power consumption.
We designed a FPGA platform to implement a full hardware-based high-speed embedded video streaming system. This system consists of two modules: a gigabit UDP/IP Offload Engine, as well as a video capture and streaming format module. The video capture and streaming module acted as a controller to capture video in the format of the CMOS camera module and to translate it into the last generated position posed by the generator package.
Our hardware-based UDP/IP Offload Engine required less hardware resources. The circuit area used was less than 3K logic units and memory requirements were 87 Kbits. This result could be beneficial to future ultra-low-cost mass produced ASIC chips. In addition, the 125MHz system clock in the FPGA platform was able to achieve gigabit class network data streaming performance and could be used to address traditional microprocessor performance bottlenecks.

[1] Andreas Löfgren Lucas Lodesten Stefan Sjöholm,”An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity,” NORCHIP Conference, 23rd, 2005
[2] Herrmann, F.L.; Perin, G.; de Freitas, J.P.J.; Bertagnolli, R.; dos Santos Martins, J.B.; “AN UDP/IP NETWORK STACK IN FPGA”, Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on Digital Object Identifier: 10.1109/ICECS.2009.5410757, pp. 836 – 839, 2009
[3] Z.-Z. Wu, H.-C. Chen, “Design and Implementation of TCP/IP Offload Engine System over Gigabit Ethernet,” IEEE Proc. Of 15th International Conference on Computer Communications and Network, pp245-250, 2006.
[4] “TCP/IP offload Engine (TOE) — Carrier Metro Ethernet Broadband, WAN, WDM WaveLengths, Fiber and Ethernet Whitepapers”, [Online]. Available: http://www.10gea.org/tcp-ip-offload-engine-toe/.
[5] James F. Kurose, Keith W. Ross, “Computer Networking: A Top-Down Approach,” 5th Edition, March 31, 2009.
[6] Behrouz A. Forouzan, Sophia Chung Fegan, “TCP/IP Protocol Suite,” 3rd Edition, ISBN 0-07-246060-1.
[7] J. Postel, “User Datagram Protocol,” RFC 768 (Stan-dard), Internet Engineering Task Force, August 1980.
[8] J. Postel, “Internet Protocol,” RFC 791 (Standard), In-ternet Engineering Task Force, September 1981. (Up-dated by RFC 1349).
[9] “IEEE 802.3 ETHERNET”, [Online]. Available: http://www.ieee802.org/3/.
[10] Sandhya Senapathi, Rich Hernandez,"Introduction to TCP Offload Engines", [Online]. Available: http://www.dell.com/downloads/global/power/
[11] “RFC 793 - Transmission Control Protocol (RFC793)”. [Online]. Available: http://www.faqs.org/rfcs/rfc793.html.
[12] 雷良煥,黃吉成,徐永珍, “後來居上的CMOS 影像感測器”, 物理雙月刊32 期 1 卷 2010年2月 p. 24
[13] Chen, Ching-Han; Dai, Jia_Hong; “Design and high-level synthesis of discrete-event controller”, National Conference of Automatic Control and Mechtronics System, vol.1, 2002, pp. 610–615.
[14] 郭家銘,”模糊系統高階合成”, 義守大學電機工程學系碩士學位論文,2001
[15] 杜金鴻,”機率神經網路之系統設計與高階合成”, 義守大學電機工程學系碩士學位論文,2003
[16] 王士銘,”Gigabit乙太網路的UDP/IP硬體加速器設計”, 中央大學資訊工程學系碩士學位論文,2010
[17] “Triple-Speed Ethernet MegaCore Function User Guide”, [Online]. Available: http://www.altera.com/products/ip/iup/ethernet/m-alt-ethernet-mac.html.