從1985年單電子電晶體 (single electron transistor)的概念由莫斯科大學的兩位教授提出後，由於它的高操作速度、低消耗功率，以及有別於傳統元件的量子特性，使得單電子電晶體吸引了許多研究團隊的注意。近十年來，為了和CMOS 製程技術整合，以矽基 (silicon base)半導體製作的單電子電晶體，更如雨後春筍般地相繼發表。然而，這些元件都面臨了製程再現性、關鍵尺寸不易微縮，與製程花費昂貴等問題。
在本論文中，著重於改善本實驗室過去以低壓化學氣相系統 (low pressure chemical vapor deposition system)將複晶矽鍺沉積在絕緣層上碰到的沉積率太快、薄膜表面起伏過大，與薄膜中鍺含量過高等問題。此外，將複晶矽鍺應用到本實驗室早先開發的三端電極與鍺量子點自我對準的結構中，且佐以高解析度的穿透式電子顯微鏡觀察，提出選擇性氧化複晶矽鍺合金自我形成鍺量子點與穿隧接面的直接證據。根據穿透式電子顯微鏡影像，本論文觀察到，鍺量子的顆數與閘長度間具有很強的相依性。當閘長度小於40 nm 時僅會形成單一一顆鍺量子點，但當閘長度大於40 nm時，則會形成一顆或兩顆的鍺量子點。最後以電子顯微鏡影像搭配模擬對奈米結構的氧化過程進行分析。

Since the first concept of single electron transistor (SET) was proposed by Likharev et al. in Moscow University at 1985, SETs have attracted a lot of attention due to their high speed, ultralow power consumption, and unique quantum characteristics. In decades, many researchers have developed the cutting-edge fabrication technology for silicon based SETs in complementary metal-oxide-semiconductor (CMOS) compatible processes. However, all these devices face the issue of reproducibility, scalability and high cost issues.
The main theme of this thesis is to improve the process parameters such as deposition rate, surface roughness and germanium mole fraction of poly-SiGe on insulator using low pressure chemical vapor deposition (LPCVD) technique. Consequently, we could apply the developed poly-SiGe films into a self-aligned SET structure, which has been proposed and demonstrated. We have used transmission electron microscopy (TEM) to verify the existence and number of self-assembled germanium quantum dot and tunneling barriers widths. We found that only one Ge quantum dots embedded in oxide matrix when channel length less than 40 nm, while one or two Ge quantum dot(s) for the channel length larger than 40 nm. The results are well explained by simulated oxidation contour of nano-structure using T-suprem4.

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