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研究生： 王榮顯
Rong-sain Wang
論文名稱： 可支援4x4 MIMO系統之高速且低複雜度Sorted QR分解
Design of High Speed and Low Complexity Sorted QR Decomposition for 4x4 MIMO Detectors
指導教授： 薛木添
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 中文
論文頁數： 87
中文關鍵詞： QR分解 、MIMO 、排序
外文關鍵詞： QRD, MIMO, Sort
相關次數： 點閱：11  下載：0 
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    • 本論文以降低傳統Systolic Sorted QR分解的運算成本為研究目標。我們深入的研究了QR分解在Systolic架構下造成的CORDIC閒置問題以及傳統模擬不夠仔細下造成的Word-Length遷就問題。我們提出了CORDIC Reusing設計以利大幅的縮減硬體面積並增加CORDIC使用率，藉由仔細的硬體模擬而排除了不必要的Word-Length遷就，再搭配刪除不必要之排序級數來縮減排序電路。本論文以4x4 MIMO系統的需求設計了高速且低複雜度的Modified Systolic Sorted QR分解電路，相較於傳統之Systolic Sorted QR分解，本論文所呈現的硬體總縮減量高達33.8%。最後使用TSMC-90 nm製程來實現所設計之電路，以驗證所提出之電路設計措施的有效性。

    The research objective of this treatise is to reduce the computational cost of traditional systolic sorted QR decomposition. We had studied two kinds of issue in traditional systolic sorted QR decomposition. One is the CORDIC Idling which is caused by systolic architecture and the other is the Word-Length Compromising resulted from the un-careful simulation. We propose the CORDIC Reusing method which can reduce circuit area effectively and increase CORDIC utilization,carefullyconductsimulation to achieve no unnecessary word-length compromising, andcoordinate the Sort Reduction method to reduce the complexity of sorting circuit without BER performance loss. In this treatise, we present a high-speed and low complexitymodifiedsystolic sorted QR decomposition for 4 × 4 MIMO detector. Comparing with traditional systolic sorted QR decomposition, our circuit has an enormous reduction of 33.8%. In the end, we use TSMC-90 nm to implement our design.

    摘要 i Abstract ii 致謝 iii 目錄 iv 圖目錄 v 表目錄 vi 第一章緒論 1 1.1研究背景 1 1.2研究動機 2 1.3論文架構 2 第二章SortedQR分解介紹 3 2.1 MIMO系統 3 2.2實數分解 4 2.3 QR分解 4 2.3.1 QR分解的演算法介紹(Givens Rotation) 5 2.4以CORDIC實現Givens Rotation 7 2.4.1 Systolic-CORDIC QR分解 9 2.5 Sorted QR分解 9 第三章所提出之Sorted QR分解 11 3.1傳統Systolic Sorted QR分解 11 3.2所提出之Sorted QR分解 12 3.3 Sort Reduction 13 3.3.1 Sort Reduction演算法 13 3.3.2 Sort Reduction運用於本論文之4x4 SQRD 14 3.4 CORDIC Reusing 16 3.4.1 CORDIC Reusing演算法 16 3.4.2 CORDIC Reusing運用於本論文之4x4 SQRD 23 3.5 CORDIC Word-Length Reduction 24 3.5.1 CORDIC Word-Length Reduction演算法 24 3.5.2 CORDIC Word-Length Reduction運用於本論文之4x4 SQRD 25 第四章所提出之Sorted QR分解電路設計 27 4.1電路架構 27 4.2 Sorting 電路設計 28 4.2.1 CPC電路設計 29 4.2.2 SG電路設計 30 4.2.3 SB電路設計 31 4.2.4 SR電路設計 32 4.3Modified Systolic CORDIC Array電路設計 33 4.3.1 CORDIC電路設計 34 4.3.2 Control、CIC及RYS電路設計 35 第五章晶片實現 38 5.1 設計流程 38 5.2 定點數分析 39 5.3晶片設計結果 44 5.4硬體比較 49 第六章結論 50 參考文獻 附錄I 附錄II

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