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研究生: 張櫂祺
Chao-Chi Chang
論文名稱: 應用於TCP資料傳輸之AMP雙核心感測系統設計與實作
指導教授: 董必正
Pi-Cheng Tung
口試委員:
學位類別: 碩士
Master
系所名稱: 工學院 - 機械工程學系
Department of Mechanical Engineering
論文出版年: 2025
畢業學年度: 113
語文別: 中文
論文頁數: 85
中文關鍵詞: FPGAZynq-7000 SoCOpenAMP非對稱多核心(AMP)
外文關鍵詞: FPGA, Zynq-7000 SoC, OpenAMP, Asymmetric multiprocessing (AMP)
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  • 隨著感測技術與邊緣運算需求提升,嵌入式系統在即時資料處理與高速通訊上的設計挑戰日益增加。為此,本研究提出一套基於 Zynq-7000 系列SoC的AMP(非對稱多核心)雙核心嵌入式架構,結合裸機與 Linux 作業環境,以達成高速資料擷取與即時網路傳輸之應用目標。
    在本研究的系統設計中,CPU1(裸機)負責控制Zmod ADC 1410 模組,透過 AXI DMA 將資料搬移至 OCM;CPU0(Linux)則透過 mmap 讀取 OCM 資料,並透過TCP將資料傳送至遠端伺服器。雙核心間採用 OpenAMP 通訊機制,實作 RPMsg 虛擬訊息通道,並搭配自訂核心驅動簡化資料交換流程。
    本研究完成系統整合與多項測試,包括 OCM 傳輸效能、同步延遲與 TCP 穩定性等,結果顯示本系統具備良好之即時性與擴充彈性,適用於工業感測、智慧裝置等高速資料處理應用場域,亦為多核心嵌入式系統整合提供實用參考。


    With the advancement of sensing technologies and the growing demand for edge computing, embedded systems face increasing design challenges in real-time data processing and high-speed communication. To address this, this study proposes an AMP (Asymmetric Multiprocessing) dual-core embedded architecture based on the Zynq-7000 series SoC. By combining bare-metal and Linux environments, the system aims to achieve high-speed data acquisition and real-time network transmission.
    In the system design presented in this study, CPU1 (bare-metal) is responsible for controlling the Zmod ADC 1410 module and transferring data to OCM via AXI DMA. CPU0 (Linux) reads the OCM data through mmap and transmits it to a remote server over TCP. Communication between the two cores is handled using the OpenAMP framework, implementing an RPMsg virtual messaging channel along with a custom kernel driver to simplify the data exchange process.
    The study completes full system integration and conducts multiple tests, including OCM transfer performance, synchronization latency, and TCP stability. Results demonstrate that the system offers strong real-time performance and flexible scalability, making it suitable for high-speed data processing applications such as industrial sensing and smart devices. It also provides practical insights for integrating multi-core embedded systems.

    摘要 i Abstract ii 目錄 iv 圖目錄 vii 表目錄 ix 第一章 緒論 1 1-1. 研究背景 1 1-2. 研究動機 2 1-3. 研究目的 3 1-4. 文章架構 3 第二章 文獻回顧 5 第三章 系統運作原理與使用之硬體 10 3-1. FPGA硬體邏輯架構 10 3-1-1. FPGA架構簡介 10 3-1-2. 預建XSA硬件平台介紹 11 3-2. TCP/IP傳輸協定介紹 13 3-3. 硬體設備介紹 16 3-3-1. Eclypse Z7 | FPGA開發板 16 3-3-2. Zmod ADC 1410 | 類比數位轉換器模組 19 3-3-3. Askey RTL0310 5G NR CPE | 無線家庭路由器 21 3-3-4. GW Instek GFG-8019G | 訊號產生器 22 第四章 系統建置內容與方法 23 4-1. 本研究之AMP系統架構設計 23 4-2. 實驗平台架構 25 4-3. 系統開發分層說明 26 4-4. CPU1(裸機)程式開發與設計 28 4-4-1. 開發工具―Vitis介紹與建置方法 28 4-4-2. Zmod ADC資料擷取流程與輪詢控制機制 30 4-4-3. 程式設計與運行流程 32 4-5. CPU0(Linux)系統開發與設計 34 4-5-1. 嵌入式系統與作業系統分層概念 34 4-5-2. 開發工具―PetaLinux介紹與建置方法 36 4-5-3. 系統配置與應用設計說明 37 4-5-4. 應用程式設計與運行流程 41 4-5-5. 自訂 RPMsg 驅動整合設計 44 4-6. OpenAMP雙核心通訊流程設計 46 4-6-1. OpenAMP架構簡介 46 4-6-2. 雙核心間資料交換與通訊同步流程 48 4-6-3. 本研究配置之資源表與雙核心同步流程設計 49 4-7. 系統效能測試設計 52 4-7-1. 實驗一:共享記憶體傳輸效能測試 53 4-7-2. 實驗二:雙核心AMP傳輸延遲測試 54 4-7-3. 實驗三:系統無線傳輸流程延遲測試 56 4-7-4. 實驗四:Zmod ADC之整體資料通路延遲測試 57 第五章 研究結果與討論 58 5-1. 共享資源傳輸效能測試 58 5-2. 雙核心AMP傳輸延遲測試 63 5-3. 系統無線傳輸流程延遲測試 65 5-4. Zmod ADC之整體資料通路延遲測試 67 第六章 結論與未來展望 69 6-1. 結論 69 6-2. 未來展望 70 第七章 參考文獻 71

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