可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計

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研究生：	楊耀先 Yao-Xian Yang
論文名稱：	可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計 Design of Self-Testable and Cost-Efficient Memory-Based FFT Processors
指導教授：	李進福 Jin-Fu Li
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	95
語文別：	英文
論文頁數：	80
中文關鍵詞：	內建自我測試電路、記憶體式快速傅利葉轉換
外文關鍵詞：	BIST, Memory-Based FFT
相關次數：	點閱：8 下載：0
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快速傅利葉轉換處理器已被廣泛的使用在各種數位領域中，如通訊系統和數位訊號處理器等等。記憶體式快速傅利葉轉換處理器是針對低成本應用所衍生出來一種熱門的設計方式，本論文將針對此技術提出一具成本效益之記憶體式快速傅利葉轉換處理器。跟現存處理器的相異之處在於所提出的處理器利用單埠記憶體做為資料存取，進而取代典型記憶體式傅利葉處理器利用雙埠記憶體的設計方式。此提出之方法將能大大的降低處理器在面積上之消耗，此外單埠記憶體的使用無論在功率消耗或是測試時間上，比起雙埠記憶體的使用將能有效的降低。
另一方面，本論文也針對記憶體式之傅利葉轉換處理器提出一內建自我測試的方法，此內建測試能夠提供邏輯和記憶體上的電路測試。與現存的方法相比，我們的內建測試設計有較低之面積需求和較低延遲之衝擊。
我們利用提出的快速傅利葉的架構搭配內建的測試設計，以256/1024點數來實現此可自我測試之記憶體式快速傅利葉轉換處理器。此實驗使用TSMC 0.18um standard cell library來進行模擬，整個可自我測試之傅利葉處理器的面積只需1.72x1.72 mm^2。

Fast-Fourier transform (FFT) processor is widely used in digital systems, such as communication, digital signal processing (DSP), etc. The memory-based FFT processor is one popular design style for low-cost applications. This thesis proposes a cost-efficient memory-based FFT processor. Differing from the existing memory-based FFT processors, the proposed memory-based FFT processor uses single-port RAMs for data buffering instead of using two-port RAMs. Therefore, the area of the proposed memory-based FFT processor can drastically be reduced. Also, the power consumption and testing cost of single-port RAMs are much less than those of two-port RAMs.
On the other hand, this thesis also proposes a built-in self-test scheme (BIST) for memory-based FFT processors. The BIST can support the testing of logic circuits and RAMs. Comparing with the existing approach, our BIST scheme has the advantages of low area cost and small delay penalty.
We realized a 256/1024-point self-testable memory-based FFT processor using the proposed FFT architecture and BIST scheme. The area cost of the self-testable memory-based FFT processor is only about 1.72x1.72 mm^2, where TSMC 0.18 um standard cell library is used.

Chapter 1	 Introduction..1
Chapter 2	 Overview of Memory-Based FFT Processors..4
1	FFT algorithm..4
1.1	Discrete Fourier Transform..4
1.2	Decimation-In-Frequency Radix-2 FFT Algorithm..5
1.3	Decimation-In-Time Radix-2 FFT Algorithm..9
1.4	Radix-4 FFT Algorithm..10
2	Various Memory-Based FFT Processors..13
2.1	FFT Processors with 1.5N-bit Two-Port RAMs..13
2.2	FFT Processors with 2.5N-bit Two-Port RAMs..15
2.3	FFT Processors with 1.25N-bit Two-Port RAMs.16
2.4	FFT Processors with 1N-bit Two-Port (Single-Port) RAMs..18
Chapter 3	 Proposed Memory-Based FFT Processors..20
1	Architecture of the Proposed SPMFFT Processor.20
2	The Controller of SPMFFT Processor..26
2.1	Generation of RAM Control Signals..26
2.2	Control Signals for Multiplexers and Adders..34
2.3	Control Signals for the ROM..38
3.4	Design-for-Reconfigurability Control..40
3	Analysis and Comparison Results..40
Chapter 4 A Built-In Self-Test Scheme for Memory-Based
FFT Processors..44
1	Introduction..44
2	Previous Work..44
3	BIST Scheme..47
3.1	Integration of the BIST Scheme and the SPMFFT Processor	..49
3.2	The BIST Structure..51
4	Analysis and Comparison..58
Chapter 5	 Test Chip of a 256/1024-point SPMFFT Processor.61
1	Design Flow..61
2	Verification..62
3	Synthesis Results..64
3.1	Gate-Level Simulation..65
3.2	Power Analysis..69
4	Placement and Routing..69
5	Post-Layout Simulation..71
6	Comparison Results..73
Chapter 6	 Conclusions and Future Works..76
Reference	..77

                                

[1] E. Bidet, D. Castelain, C. Joanblanq, and P. Senn, ”A fast single-chip implementation of 8192 complex point FFT”, IEEE Journal of Solid-State Circuits, pp. 300-305, March 1995.
[2] M. Hasan, T. Arslan, and J.S. Thompson, ”A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications”, IEEE Tran. on Consumer Electronics, pp.128-134, Feb. 2003.
[3] C.-C. Wang, J.-M. Huang, and H.-C. Cheng, ”A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers”, IEEE Trans. on Consumer Electronics, vol. 51, no. 1, pp.28-32, Feb. 2005.
[4] L. Yang, K. Zhang, H. Liu, J. Huang, and S. Huang, ”An efficient locally pipelined FFT processor”, IEEE Tran. on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp.585 – 589, July 2006.
[5] S.-K. Lu, J.-C. Wang, and C.-W. Wu, ”C-testable design techniques for iterative logic arrays”, IEEE Tran. on Very Large Scale Integration (VLSI) Systems ,vol. 3, no. 1, pp.146 – 152, March 1995.
[6] J.-F. Li and C.-W. Wu, ”Testable and fault tolerant design for FFT networks”, in Proc. Int. Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 1999, pp.201 – 209.
[7] J.-F. Li, S.-K. Lu, S.-A. Hwang, and C.-W. Wu, ”Easily testable and fault-tolerant FFT butterfly networks”, IEEE Tran. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 9, pp.919-929, Sept. 2000.
[8] J.-F. Li and C.-W. Wu, ”Efficient FFT network testing and diagnosis schemes”, IEEE Tran. on Very Large Scale Integration (VLSI) Systems, Vol. 10, no. 3, pp.267 – 278, June 2002.
[9] C.-H. Chang, C.-L. Wang, and Y.-T. Chang, “A novel memory-based FFT processor for DMT/OFDM applications”, in Proc. IEEE Int. Conf. on Acoustics, Speech, Signal Processing, March 1999, pp. 3206-3216.
[10] C.-L. Wang and C.-H. Chang, “A new memory-based FFT processor for VDSL transceivers”, in Proc. IEEE International Symposium on Circuits and Systems, May 2001, pp. 670-673.
[11] C.-K. Chang, C.-P. Hung, and S.-G. Chen, “An efficient memory-based FFT architecture”, in Proc. Int. Symposium on Circuit and Systems (ISCAS), May 2003, pp. II-129 - II-132.
[12] S.-C. Moon and I.-C. Park, ”Area-efficient memory-based architecture for FFT processing”, in Proc. Int. Symposium on Circuit and Systems (ISCAS), May 2003, pp. V101 - V104.
[13] L. Jia, Y. Gao, and H. Tenhunen, ”Efficient VLSI implementation of radix-8 FFT algorithm”, in Proc. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Aug. 1999, pp.468 – 471.
[14] S.-Y. Lee, C.-C. Chen, C.-C Lee, and C.-J. Cheng,” A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme”, in Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2006, pp.157 – 160.
[15] Y. Zhao, A.T. Erdogan, and T. Arslan, ”A novel low-power reconfigurable FFT processor”, in Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2005, pp.41 – 44.
[16] H. Jiang, H. Luo, J. Tian, and W. Song, ”Design of an efficient FFT Processor for OFDM systems”, IEEE Tran. on Consumer Electronics, vol. 51, no. 4, pp.1099 – 1103, Nov. 2005.
[17] B. G. Jo and M. H. Sunwoo, ”New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy”, IEEE Tran. on Circuits and Systems I: Regular Papers, vol. 52, no. 5, pp.911 – 919, May 2005.
[18] S.-K. Lu, C.-H. Yeh, and H.-W. Lin, “Efficient built-in self-test techniques for memory-based FFT processors”, in Proc. IEEE Pacific Rim International Symposium on Dependable Computing, March 2004, pp.321 – 326.
[19] Y. Zhao, A.T. Erdogan, and T. Arslan, ”A low-power and domain-specific reconfigurable FFT fabric for system-on-chip applications”, in Proc. 19th IEEE Int. Parallel and Distributed Processing Symposium, April 2005, pp.4.
[20] C.-H. Chang, C.-L. Wang, and Y.-T. Chang, “Efficient VLSI architectures for fast computation of the discrete Fourier transform and its inverse”, IEEE Tran. on Acoustics, Speech, and Signal Processing, vol.48, Issue 11, pp.3206-3216, Nov. 2000.
[21] C.-W. Wang, K.-L. Cheng, C-T. Huang, and C.-W. Wu, “Test and diagnosis of word-oriented multiport memories”, in Proc. IEEE VLSI Test Symposium (VTS), April-May 2003, pp.248 – 253.
[22] J. Zhao, S. Irrinki, M. Puri, and F. Lombardi, ”Detection of inter-port faults in multi-port static RAMs”, in Proc. IEEE VLSI Test Symposium, May 2005, pp.297-302.
[23] C.-F. Wu, C.-T. Huang, and C.-W. Wu, ”RAMSES: a fast memory fault simulator,” in Proc. IEEE Int’s Symp. On Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165-173.
[24] J. W. Cooley and J. W. Tukey, “An algorithm for machine computation of complex Fourier series”, in Proc. Math. Computation, vol.19, April 1965, pp. 297–301.
[25] G.-D. Wu and Y. Lei, “Low power pipelined radix-2 FFT processor for speech recognition”, IEEE/SMC Int.Conf. on System of Systems Engineering, April 2006. pp. 299–303.
[26] Y.-H. Lee, T.-H. Yu, K.-K. Huang, and A.-Y. Wu, “Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems”, in Proc. IEEE Workshop on Signal Processing Systems Design and Implementation, Oct 2006, pp. 62 – 65.
[27] A. V. Oppenheim, R. W. Schafer, and J. R. Buck, “Discrete-Time Signal Processing (2nd Edition)”, Feb 1999.
[28] H.-F. Lo, M.-D. Shieh, and C.-M. Wu, “Design of an efficient FFT processor for DAB system”, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol.4, May 2001, pp.654 – 657.
[29] P.-Y. Tsai, T.-H. Lee, and T.-D. Chiueh, “Power-Efficient Continuous-Flow Memory-Based FFT Processor for WiMax OFDM Mode”, in Proc. Int. Symposium on Intelligent Signal Processing and Communications (ISPACS), Dec. 2006, pp.622-625.
[30] C.-L. Wey, W.-C. Tang, and S.-Y. Lin, “Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications”, in Proc. IEEE Computer Society Annual Symposium on VLSI, March 2007 pp.98-106.
[31] C.-L. Wey, W.-C. Tang, and S.-Y. Lin, “Efficient Memory-Based FFT Architectures for Digital Video Broadcasting (DVB-T/H)”, in Proc. Int. Symposium on VLSI Design, Automation and Test, April 2007, pp.1-4.
[32] S. Lee, H. Kim, and S.-C. Park, “Design of Power-efficient Memory-based FFT Processor with New Memory Addressing Scheme”, in Proc. Asia-Pacific Conference on Communications, Aug. 2006, pp.1-5.
[33] A. Delaruelle, J. Huisken, J. van Loon, F. Welten, “A channel demodulator IC for digital audio broadcasting”, in Proc. IEEE Custom Integrated Circuits Conference, May 1994, pp.47-50.

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