包含通道追蹤之IEEE 802.11a接收機設計與電路實現

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研究生：	林宗賢 Zong-Sian Lin
論文名稱：	包含通道追蹤之IEEE 802.11a接收機設計與電路實現 Design and Implementation of the IEEE 802.11a Receiver with Channel Tracking
指導教授：	張大中 Dah-Chung Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 通訊工程學系 Department of Communication Engineering
畢業學年度：	93
語文別：	中文
論文頁數：	63
中文關鍵詞：	正交分頻多工、無線接收機、通道追蹤
外文關鍵詞：	OFDM, Wireless LAN, 802.11a, Channel Tracking
相關次數：	點閱：4 下載：0
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摘要
IEEE802.11a 系統是一無線傳輸的通訊系統，使用正交分頻多工調變(Orthogonal Frequency Division Multiplexing，OFDM)來增加傳輸的頻寬效益，也具有一般OFDM 系統所包含的多重路徑干擾(Multipath Channel)、載波頻率偏移(Carrier Frequency Offset)
等問題。
本篇論文利用FPGA 實現IEEE 802.11a 實體層，並在演算法方面探討載波頻率偏移、時序偏移、以及多重路徑干擾對於接收端的影響，也加入通道追蹤(Channel Tracking)模組來增進系統的效能。我們先以VHDL 驗證完成後，再以Xilinx FPGA 及邏輯分析儀作整體硬體上的驗證與分析，最後得到理論與實現上之印證。

Abstract
IEEE802.11a is a wireless communication system based on Orthogonal Frequency Division Multiplexing (OFDM) modulation to increase the bandwidth efficiently. As a general OFDM system, it also suffers from inter-carrier interference (ICI) and the inter-symbol interference (ISI) caused by the multipath channel, carrier frequency offset…, etc.
This thesis implements the IEEE 802.11a physical layer on FPGA and explores the carrier frequency offset, timing offset, and the effect caused by multipath channels in the algorithm-level. The channel tracking module is also included to improve the system performance. The VHDL design is verified by the FPGA board. The LA (Logic Analyzer) is used to grab the output data for analysis to achieve a comprehensive study.

序論.............................................. 1
1. 前言.......................................... 1
2. 研究動機...................................... 2
OFDM 系統與802.11a 標準介紹....................... 4
1.OFDM 簡介......................................... 4
2.802.11a 標準...................................... 6
3.多路徑通道成因.................................... 9
系統模擬與設計................................... 11
1. 接收機之同步問題與演算法...................... 11
1.1. 802.11a 系統的同步問題................. 11
1.1.1.時序同步問題的影響............. 11
1.1.2.載波不同步造成的影響........... 14
1.2. 時序同步............................... 16
1.2.1.封包偵測....................... 16
1.2.2.符號起點估計................... 18
1.3. 載波同步............................... 20
1.3.1.使用Preamble 進行載波偏移估計.. 20
1.3.2.角度誤差追蹤................... 21
2. 通道響應估計演算法........................... 22
2.1. 使用Preamble 進行通道估計.............. 22
2.2. 通道估計追蹤........................... 24
接收機硬體設計與實現............................. 27
1.同步相關模組設計................................. 27
1.1.封包偵測電路.............................. 28
1.2.信號符緣偵測電路.......................... 28
1.3.載波偏移估測與補償電路.................... 30
1.3.1.Cordic 演算法..................... 31
1.3.2.角度誤差補償電路................. 312
2.通道回復相關模組設計............................. 33
2.1.fft 模組使用與輸出緩衝區的設計............. 33
2.2.除法器設計原理............................ 37
系統完整硬體驗証................................. 39
1.模擬環境與測試平台.............................. 39
2.系統合成結果.................................... 40
3.Download 電路與邏輯分析儀驗證結果............... 44
結論與未來工作................................... 49
Reference ........................................... 50

                                

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51
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