本論文主旨在研究以具有高介電常數的氧化鋯(ZrO2)薄膜，作為金氧半電容器(MOSC)之介電層，以取代傳統使用的二氧化矽(SiO2)，並藉由金氧半電容之電性及材料分析結果，將氧化鋯薄膜應用於製作鍺鰭式電晶體元件(Ge FinFET)。利用「加熱式原子層沉積系統沉積含有高介電常數及寬能隙的氧化鋯(ZrO2)薄膜應用於製作金氧半電容器(MOSC)及鍺鰭式電晶體元件(Ge FinFET)」，並探討其薄膜電性及相關材料特性。
　　實驗試片之特性量測與分析則包含：
(1)利用電容-電壓(C-V)與電流-電壓(I-V)特性曲線，萃取薄膜的界面缺陷密度與等效氧化厚度(EOT)，並探討MOSC元件的漏電流與散射效應。
(2)利用TEM觀察介電層的厚度及薄膜與基板之間的介面品質。
(3)利用XPS進行表面化學態分析，以了解氧化鍺(GeOx)介面層在氧化鋯介電層與鍺基板之組成關係。
在本研究中，以加熱式原子層沉積系統沉積氧化鋯薄膜，並探討沉積薄膜時表面處理的影響，其鍺鰭式電晶體元件的次臨界擺幅與導通電流比雖仍無法與文獻之最佳結果比擬，但在金氧半元件的等效氧化厚度、界面缺陷密度、漏電流與射散特性方面，則有較佳的表現；故未來研究規劃將持續針對薄膜製程進行改善，並積極開發新的高介電材料。

The purposes of this thesis is to research the physical and electrical characteristics of MOS-Capacitor on germanium (Ge) with high-κ gate oxide (ZrO2). Moreover, the Ge FinFET are also attempting to fabricate by ZrO2 MOS-Capacitor results. The Rare-earth metal-oxide (ZrO2), that has high dielectric constant and wide bandgap, was deposited by thermal atomic layer deposition. The ZrO2 MOS-Capacitor and Ge GAA-FETs are also conferred by electro property and similar material property.
ZrO2 samples were analyzed and discussed by the following measurements:
(1)C-V and I-V curves: extract interface trap density, equivalent oxide thickness, leakage current, and dispersion effect.
(2)TEM: measure film thickness and film/substrate interface quality.
(3)XPS: this work explores how using the GeOx as the interlayer was the material chemical property was formed between ZrO2 and Ge substrate.
In this study, a ZrO2 film was deposited by the thermal atomic layer deposition system and the effect of surface treatment on the deposited film was investigated Though the sub-threshold swing (S.S.) and on-off current ratio (Ion/Ioff) of ZrO2 Ge FinFET are still not well enough than reported papers, thinner equivalent oxide thickness, low leakage current, low interface trap density and low dispersion effect are obtained. Follow-up research will be continued to further improve the characteristics of ZrO2 gate dielectric on Ge FinFET.

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