有鑒於現今的單晶片系統設計，在晶片中，彙整大量的電路以及包含整個時脈訊號的分佈網絡，因此同步系統時脈將是一個重要的考量。鎖相迴路（Phase-Locked Loop，PLL）以及延遲鎖定迴路（Delay- Locked Loop，DLL）已經普遍地被應用在許多同步時脈相依的電路系統之中，以抑制時脈偏斜的情況發生。然而兩者的閉迴路特性，需要冗長的鎖定時間，在相位捕獲的過程時，需要大量的standby current，而產生較多的功率消耗。
本論文提出了兩種快速時脈同步電路，分別為任意責任週期之同步映射延遲電路以及高解析度之任意責任週期之同步映射延遲電路。我們也已驗證並證實其可行性，結果顯示此電路較過去相似之架構具相當之改善，並對那些具有高速同步需求之電路具相當之實用性。
因此，本論文所提出之電路除了能夠廣泛的被應用於記憶體時脈同步模組中，亦可整合應用在針對ASIC設計的高速時脈同步電路模組裡。

In view of the current SOC systems, a great deal of circuits is integrated on a chip and the clock signal is entirely distributed. The clock synchronization, therefore, becomes truly an important issue on it. Phase-locked loop (PLLs) and delay-locked loop (DLLs) are often applied in many synchronization- dependent systems in order to suppress the clock skew. However, both PLLs and DLLs are the feedback systems and hence requiring a long locking time. During the lock-in frequency acquisition process, it results in a large standby current, which causes lots of power dissipation.
In this study, two fast synchronization circuits have been proposed, an arbitrary duty-cycle synchronous mirror delay and a high-resolution arbitrary duty-cycle synchronous mirror delay. We have already verified and demonstrated their workability. The results show an excellent improvement over the prior works and also states that they are quite useful to that has great urgency for the higher-speed synchronization devices. Thus, the proposed arbitrary duty-cycle SMD can be not only widely applied in the memory synchronous chip module but also applied in the high speed synchronous chip module for current ASIC design.

[1]T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, and T. Okuda, “A 2.5-ns clock access, 250MHz, 256Mb SDRAM with synchronous mirror delay,” in ISSCC1996 Dig.Tech. Papers, pp. 374–375, Feb. 1996.
[2]Guang-Kaai Dehng, June-Ming Hsu, Ching-Yuan Yang and Shen-Iuan Liu, “Clock-deskew buffer using a SAR-controlled delaylocked loop,” IEEE J. Solid-State Circuits, vol. 35, pp. 1128–1136, Aug. 2000.
[3]B. Razavi, ”Design of Analog CMOS Integrated Circuit,” New York: McGraw-Hill, 2001.
[4]Sei Hyung Jang, “A new synchronous mirror delay with an auto-skew-generation circuit,” IEEE ISCAS, Vol. 5, pp. 397-400, May. 2003.
[5]Kihyuk Sung, Byung-Do Yang, and Lee-Sup Kim, “Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme,” in Proc. IEEE Int. Symp. Circuits and Systems, Vol. 3, pp. 671–674, May. 2002.
[6]T. Seaeki, H. Nakamura, and J. Shimizu, “A 10 ps jitter 2 clock cycle lock time CMOS digital clock generator based on an interleaved synchronous mirror delay scheme,” in Symp. VLSI Circuits Dig. Tech. Papers, pp. 109–110, Jun. 1997.
[7]T. Saeli, K. Minami, H. Yoshida, and H. Suzuki, “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits,”IEEE J. Solid-State Circuits, vol. 34, no 3, pp. 372–379, Mar. 1999.
[8]Yi-Ming Wang, Jinn-Shyan Wang, “A low-power half-delay-line fast skew-compensation circuit,”IEEE J. Solid-State Circuits, vol. 39, pp. 906–918, Jun. 2004.
[9]Kuo-Hsing Cheng, Chen-Lung Wu, Yu-Lung Lo and Chia-Wei Su, “A Phase-Detect Synchronous Mirror Delay for Clock Skew-Compensation Circuits” IEEE ISCAS, Vol. 2, pp. 1070-1073, May. 2005.
[10]Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, and Wonchan Kim, “An analog synchronous mirror delay for high-speed DRAM application,” IEEE J. Solid-State Circuits, vol. 34, no 4, pp. 484-493, Apr. 1999.
[11]Daeyun Shim, Yeon-Jae Jung, Seung-Wook Lee, and Wonchan Kim, “Fast locking clock generator using analog synchronous mirror delay technique with feedback control,” Solid-State and Integrated-Circuits Technology, vol. 2, pp. 1125-1127, Oct. 2001.
[12]Seong-Jin Jang, Young-Hyun Jun, Jae-Goo Lee, and Bai-Sun Kon, “ASMD with duty cycle correction scheme for high-speed DRAM,” Electronics Letters, Vol. 37, no.16, pp. 1004-1006, Aug. 2001
[13]Kihyuk Sung and Lee-Sup Kim, “A High-Resolution Synchronous Mirror Delay Using Successive Approximation Register” IEEE J. Solid-State Circuits, vol. 39, no 11, pp. 1997–2004, Nov. 1999.
[14]B. Garlepp et al., “A portable digital DLL for high-speed CMOS interface circuit,” IEEE J. Solid-State Circuits, vol. 34, pp. 632–643, May. 1999.
[15]A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters,” Electron. Lett., vol. 32, no. 12, p. 1055–1057, June 1996.
[16]K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura, M. Yamashina, “A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO,” IEEE Int. Custom Circuits Conf., pp. 213-216, May 2001.
[17]R. Holzer, “A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 2, pp. 220-482, Feb. 2002.
[18]Tae-Sung Kim, Sung-Ho Wang, and Beomsup Kim, “A low jitter, fast locking delay locked loop using measure and control scheme,” Mixed-Signal Design, SSMSD, Southwest Symposium on, pp. 45-50, Feb. 2001
[19]Jeong-Seok Chae, Daejeong Kim, and Dong Myeong Kim, “Wide range single-way-pumping synchronous mirror delay,” Electronics Letters, Vol. 36, no.11, pp. 939-940, May. 2000
[20]Kuo-Hsing Cheng, Chia-Wei Su, Chen-Lung Wu and Yu-Lung Lo, “A Phase-Locked PulseWidth Control Loop with Programmable Duty Cycle,” IEEE ASIA-PACIFIC Conference on ASIC, pp. 84-87, Aug. 2004.