隨著製程的演進，電路佈局(Layout)所產生的寄生效應對於電路效能的影響也越來越顯著，然而在傳統類比電路自動化設計工具中，元件尺寸調整與電路佈局大多分成兩個獨立的流程，因為寄生效應對於電路效能的影響並未考慮進去，導致耗費了相當多的時間重複調整設計。本篇論文提出一套考量寄生效應的類比積體電路自動化設計工具，可經由操作客製化的圖形介面，設計出符合需求規格的電路設計與電路佈局。為了讓尺寸調整與電路佈局達到最佳的連結，本論文在考量寄生效應的尺寸調整流程中，使用佈局樣板預估出寄生電阻電容值，並結合電壓驅動設計方法，避免佈局後的電路效能不符合訂定之規格。整套類比自動化工具在LINUX上實現，在線性規劃(linear programming)的部分用CPLEX來找尋最佳解，而在自動產生電路佈局上則是以C/C++及Tcl/Tk 程式語言實現，自動化佈局的過程能在Laker環境下執行。從實驗數據的觀察可知，本論文所提出的工具可以在非常短的時間內設計出符合使用者所給定規格之電路與最佳的擺放佈局，並在佈局後電路效能皆有達到訂定規格的標準，且不需預留設計的邊界。

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this thesis, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. The proposed sizing algorithm has been implemented with the optimization tool CPLEX, incorporating with an automatic layout generation tool implemented with C/C++ and Tcl/Tk on Laker. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

[1] R. A. Rutenbar, G. G. E. Gielen, and J. Roychowdhury, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs,” in Proc. of the IEEE, pp. 640-669, 2007.
[2] F. El-Turky and E.E. Perry, “BLADES: An Artificial Intelligence Approach to Analog Circuit Design”, IEEE Trans. on Computer-Aided Design, pp. 680-692, 1989.
[3] J. Mahattanakul and J. Chutichatuporn, “Design Procedure for Two-Stage CMOS Op-Amp with Flexible Noise-Power Balancing Scheme”, IEEE Trans. on Circuits and Systems-I: Regular Papers, pp. 1508-1514, 2005.
[4] R. Phelps, M. Krasnicki, R. A. Rutenbar, L.R. Carley and J.R. Hellums, “Anaconda: Simulation-Based Synthesis of Analog Circuits via Stochastic Pattern Search”, IEEE Trans. on Computer-Aided Design, pp. 703-717, 2000.
[5] C.-W. Lin, P.-D. Sue, Y.-T. Shyu and S.-J. Chang, “A Bias-Driven Approach for Automated Design of Operational Amplifiers”, in Proc. Int’l Symp. on VLSI Design, Automation, and Test, pp. 119-121, 2009.
[6] M. del M. Hershenson, S. P. Boyd, and T. H. Lee, “Optimal Design of a CMOS Op-Amp via Geometric Programming”, IEEE Trans. on Computer-Aided Design, pp. 1-21, 2001.
[7] W. Gao and R. Hornsey, “A Power Optimization Method for CMOS Op-Amps Using Sub-Space Based Geometric Programming”, in Proc. DATE, pp. 508-513, 2010.
[8] M. Ranjan, W. Verhaegen, A. Agarwal, H. Sampath, R. Vemuri, G. Gielen, “Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models”, in Proc. DATE, pp. 604-609, 2004.
[9] G. Zhang, A. Dengi, R. A. Rohrer, R. A. Rutenbar, L. R. Carley, “A Synthesis Flow Toward Fast Parasitic Closure For Radio-Frequency Integrated Circuits,” in Proc. DAC, pp. 155–158, 2004.
[10] R. Castro-López, O. Guerra, E. Roca, and F. V. Fernández, “An Integrated Layout-Synthesis Approach for Analog ICs”, IEEE Trans. on Computer-Aided Design, pp. 1179-1189, 2008.
[11] H. Habal and H. Graeb, “Constraint-Based Layout-Driven Sizing of Analog Circuits”, IEEE Trans. on Computer-Aided Design, pp. 1089-1102, 2011.
[12] K. Lampaert, D. Garrod, R. Rutenbar, and L. Carley, “Koan/Anagram II: New Tools for Device-Level Analog Placement and Routing,” IEEE J. Solid-State Circuits, pp. 330-342, 1991.
[13] L. Zhang, U. Kleine and Y. Jiang, “An automated design tool for analog layouts”, IEEE Trans. on VLSI System, pp. 881-894, 2006.
[14] E. Yilmaz, Günhan Dündar “Analog Layout Generator for CMOS Circuits”, IEEE Trans. on Computer-Aided Design, pp. 32-45, 2009.
[15] A. Agarwal and R. Vemuri, “Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners”, IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), 2005
[16] M. Webb and H. Tang, “Analog Design Retargeting by Design Knowledge Reuse and Circuit Synthesis,” in Proc. International Symposium on Circuits and Systems, pp. 892–895, 2008.
[17] L. Zhang, N. Jangkrajarng, S. Bhattacharya, and C.-J. Richard Shi, “Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach”, IEEE Trans. on Computer-Aided Design, pp. 791- 802, 2008.
[18] Z. Li and L. Zhang, “A Performance-Constrained Template-Based Layout Retargeting Algorithm for Analog Integrated Circuits” Asia and South Pacific , Design Automation Conference (ASP-DAC), 2010
[19] P.-H. Lin, “Hierarchical Analog Circuit Placement,” PhD dissertation, Taiwan University, Electrical Engineering, 2009
[20] K. Lampaert, G. Gielen, and W. Sansen, “Analog Layout Generation for Performance and Manufacturability, “ Boston, MA: Kluwer, 1999.
[21] T. Sen, “Yet another simulation based sensitivity analysis tool for analog layout generation,” M.S. thesis, Bogaziçi Ünivertisesi, Istanbul, Turkey, 2007.
[22] Y.-C. Liao, Y.-L. Chen, X.-T. Cai, C.-N. Jimmy Liu, and T.-C. Chen, “LASER: layout-aware analog synthesis environment on laker”, in Proc. ACM international conference on Great lakes symposium on VLSI, pp. 107-112, 2013.
[23] Y.-F. Cheng, L.-Y. Chan, Y.-L. Chen, Y.-C. Liao, and C.-N. Jimmy Liu, “A Bias-Driven Approach to Improve the Efficiency of Automatic Design Optimization for CMOS OP-Amps”, in Proc. Asia Symposium on Quality Electronic Design, pp. 59-63, 2012.
[24] W. Gao and R. Hornsey, “A Power Optimization Method for CMOS Op-Amps Using Sub-Space Based Geometric Programming”, in Proc. Design, Automation and Test in Europe, pp. 508-513, 2010.
[25] P. Mandal, V. Visvanathan, “CMOS Op-Amp Sizing Using a Geometric Programming Formulation”, IEEE Trans. On Computer-Aided Design, pp. 22-38, 2001.
[26] ILOG CPLEXTM from IBM, http://www.ilog.com/products/cplex/
[27] LakerTM from Synopsys, http://www. synopsys.com
[28] C.-L. Hsu, “A Template-Based Layout Automation Tool for PLL Circuits,” M.S. thesis, Central University, Taiwan, 2011.
[29] Y.-C. Ding, “Template-Based Parasitic-Aware Synthesis Approach for Analog Circuits,” M.S. thesis, Central University, Taiwan, 2012.
[30] R.A Rutenbar., “Emerging Tools for Analog & Mixed-Signal: The Role of Synthesis and Analog Intellectual Property” in DATE master course, 2003
[31] Y.-F. Cheng, “A Bias-Driven OP-Amp Sizing Approach with Improved Prediction of Frequency Response and Channel Length Effects,” M.S. thesis, Central University, Taiwan, 2012.